Rockwell Automation 1785-Lxxx Enhanced and Ethernet PLC-5 Programmable Controllers - Manual (Page 317)

Publication 1785-UM012D-EN-P - July 2005
Instruction Set Quick Reference D-17
File Instructions
Bit Distribute
BTD When the input conditions are true, the controller copies the
number of bits specified by Length, starting with the Source bit
(3) of the Source (N7:3), and placing the values in the
Destination (N7:4), starting with the Destination bit (10).
Instruction Description
BTD
BIT FIELD DISTRIB
Source
Source bit
N7:3
3
0
N7:4 Dest
Dest bit
0
10
Length 6
Instruction Description
File Arithmetic and
Logic
FAL
Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
When the input conditions go from false-to-true, the
controller reads 8 elements of N14:0, and subtracts 256 (a
constant) from each element. This example shows the
result being stored in the eight elements beginning with
N15:10. The control element R6:1 controls the operation.
The Mode determines whether the controller performs the
expression on all elements in the files (ALL) per program
scan, one element in the files (INC) per false-to-true
transition, or a specific number of elements (NUM) per
scan.
The FAL instruction can perform these operations: add (+),
subtract (-), multiply (*), divide (|), convert from BCD (FRD),
convert to BCD (TOD), square root (SQR), logical and (AND),
logical or (OR), logical not (NOT), exclusive or (XOR), negate
(-), clear (0), move, and the new math instructions (see the
CPT list).
File Search and
Compare
FSC
Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
IN - Inhibit Bit
FD - Found Bit
When the input conditions go from false-to-true, the
controller performs the not-equal-to comparison on 10
elements between files B4:0 and B5:0. Mode determines
whether the controller performs the expression on all
elements in the files (ALL) per program scan, one element in
the files (INC) per false-to-true transition, or a specific
number of elements (NUM) per scan. Control element R9:0
controls the operation.
When the corresponding source elements are not equal
(element B4:4 and B5:4 in this example), the controller
stops the search and sets the found .FD and inhibit .IN bits
so your ladder program can take appropriate action. To
continue the search comparison, you must reset the .IN bit.
To see a list of the available comparisons, see the
comparisons listed under the CMP instruction.
FAL
FILE ARITH/LOGICAL
Control
Position
R6:1
0
8
ALL
Length
Mode
Dest
Expression #N15:10
#N14:0 - 256
FSC
FILE SEARCH/COMPARE
Control
Position
R9:0
0
90
10
Length
Mode
Expression #B4:0 <> #B5:0