Rockwell Automation 1785-Lxxx Enhanced and Ethernet PLC-5 Programmable Controllers - Manual (Page 359)

Publication 1785-UM012D-EN-P - July 2005
Troubleshooting F-11
Suggested Action
To avoid unexpected operation that may result from these prescan activities,
follow these guidelines:
• Do not use indexed or indirect addressing with the instructions listed in
the above table.
• If you must use indexed or indirect addressing, use the first scan bit
(S:1/15) to pre-initialize all of the other used variables.
• If using indirect addressing with any ladder instructions, do not use the
data variable holding the indirect address for multiple functions.
FOR Ladder instructions within the FOR/NXT loop are prescanned.
MSG If the SFC startover bit is cleared and the CO bit is cleared, then all
non-user configuration bits 15, 14, 13, 12, 10, and 9 are cleared in both
the INT and MG file types. The MG file type also clears bits 11, 7, 6, 5, 4,
2, 1, and 0.
ONS The programmed bit address of the instruction is set to inhibit false
triggering when the first run-mode scan begins.
OSF The programmed bit address of the instruction is cleared to inhibit false
triggering when the first run-mode scan begins. The output bit is also
cleared.
OSR
PID For PD file type, the INI bit is cleared.
INT file type clears status bits 8, 9, and 10 (deadband, upper, and lower
output alarm). The error register from the previous scan is set to 32767,
which indicates that the setpoint and ER bits from previous scans have
not yet been initialized). The Integral Accumulator and Derivative Error
bits are cleared.
SQL The EN bit is set to prevent a false increment of the table pointer when
the first run-mode scan occurs.
SQO
TOF The TT, TC, TE, and TO bits are cleared and the ACC = preset.
DTR
(1) The reference value is updated (regardless of the rung condition).
(1) The DTR instruction operates in this manner during a normal scan as well.
This
Instruction: Executes These Actions During Prescan: