Achronix ACE Version 5.0 - Manual (Page 137)

Views Chapter 3. Concepts
Post-PnR Buffer Limit max postpnr buffer limit This limit specifies the maximum
number of post-placement buffers
that can be inserted.
Post-PnR Rewiring postpnr rewire If turned on, allows post-pnr
rewiring to better the design
performance and resource usage.
Placement Effort placement effort Low effort placement will have a
shorter runtime, but may yield less
design QoR than High effort
placement. High effort placement
increases placement runtime to
further optimize the design QoR if
possible.
PnR Seed seed The place and route seed is used to
initialize random number state in
the place and route algorithms.
Asynchronous (HP) Fabric Timing Analysis Implementation Options
Option TCL Option Description
I/O Timing Analysis timing io performance Enables creation of the separate IO
Timing Report when working with
asynchronous fabrics.
Part I: Current
Performance
timing current performance Report performance for current xp
settings.
Number of Paths timing num paths part1 Maximum number of paths per
clock group for Part I.
Part II: Potential
Performance
timing potential performance Report performance for optimal xp
settings.
Make an XP Table timing search xp part2 Determine performance for different
XP values for Part II.
Number of Paths timing num paths part2 Maximum number of paths per
clock group for Part II.
Part III: Domain Details timing domain details Report per-clock performance,
without consideration of clock
relations.
Make an XP Table timing search xp part3 Determine performance for different
XP values for Part III.
Number of Paths timing num paths part3 Maximum number of paths per
clock for Part III.
Synchronous (HD) Fabric Timing Analysis Implementation Options
Option TCL Option Description
Number of
critical paths
sync timing num paths Maximum number of critical paths per clock group.
125 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012