Achronix ACE Version 5.0 User Manual

Page 57

Advertising
background image

Editors

Chapter 3. Concepts

Clock Enable Priority

Y

The Clock Enable Priority controls the relationship
between the outregce clock enable input and the
rstreg reset input during an assertion of the rstreg
signal on the output register. Setting the value to
rstreg

allows the output register to be set/reset at

the next active edge of the rdclk without requiring
a specific value on the outregce output register
clock enable input. Setting the value to regce
requires that the outregce output register clock
enable input is active for the output register
set/reset operation to occur at the next active edge
of the rdclk.

Flag Settings

Almost Full Offset (decimal)

Y

This defines the word depth at which the FIFO
almost full signal is asserted. The almost full flag
is asserted when there are (afull offset + 1) or fewer
locations available to be written in the FIFO. The
almost full signal is asserted when the the
difference between the Write Pointer and the Read
Pointer is greater than or equal to the difference
between the Maximum FIFO Depth and the value
of this field (afull offset parameter).

Almost Empty Offset
(decimal)

Y

This defines the word depth at which the FIFO
almost empty signal is asserted. The almost empty
flag is asserted when there are (aempty offset - 1)
or fewer words remaining in the FIFO. The
almost empty signal is asserted when the the
difference between the Write Pointer and the Read
Pointer is less than the value of this field
(aempty offset parameter).

Synchronize Write
Pointer/Count to Read Clock

Y

When enabled, the Write Count (wrcount) output
is synchronized to the Read Clock (rdclk) input.
Otherwise, if left unchecked, the Write Clock
output will be synchronized to the Write Clock
(wrclk) input.

Write Pointer Sync Stage
Depth

Y

The wrptr sync stages parameter defines the
number of stages used in the Write Pointer
Synchonizer circuit that synchronizes the Write
Pointer to the rdclk clock domain. When the FIFO
is in Dual Clock mode, the output of the
synchonized Write Pointer is compared to the Read
Pointer to generate the empty and almost empty
flags.

Synchronize Read
Pointer/Clock to Write Clock

Y

When enabled, the Read Count (rdcount) output is
synchronized to the Write Clock (wrclk) input.
Otherwise, if left unchecked, the Read Clock
output will be synchronized to the Read Clock
(rdclk) input.

45

http://www.achronix.com

UG001 Rev. 5.0 - 5th December 2012

Advertising