General snapshot description and architecture, 1 general snapshot description and architecture – Achronix ACE Version 5.0 User Manual
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Running the SnapShot Debugger
Chapter 4. Tasks
The following sections will further explain SnapShot and guide the user through the process.
General SnapShot Description and Architecture
The SnapShot macro samples user-signals in real time, and sends the captured data back through the
JTAG interface. The macro may also optionally send stimulus to the Design-Under-Test. The SnapShot
architecture is implemented to support the following features:
• Capture 2048 samples of data at the user clock frequency, up to 144 bits wide.
• Support up to three
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separate sequential trigger conditions on a 36-bit bus (trigger ch ), where each
bit of the bus is capable of operating on any user signal. Each trigger condition supports ”dont care”
features (masking).
• All captured data will be read back serially with respect to TCK.
• Send one 36-bit value (Stimuli ) to the Design-Under-Test during each sampling (arming) session. (The
value of Stimuli is currently specified in the
in place of the ”Trigger 3” value
for ”Pattern” prior to Arming SnapShot.)
Figure 4.17: SnapShot Macro Architecture Block Diagram for Capture Logic
The major logic blocks for the capture logic found within the SnapShot macro are:
• Trigger Detector This block receives one 36-bit word each from the trigger pattern (pattern in), dont
care sequence (mask ), and input data (channel in). For every channel in sample, this block evaluates
a corresponding match signal, called match out. If the corresponding mask bit is set high, match out
is asserted; otherwise, match out remains low, and is only asserted if the corresponding channel in
bit matches the pattern in bit. There is a sel in pin which comes from a JTAG register for selecting
between match out getting ORed or ANDed. If sel in pin is asserted high, match out is ANDed; if
sel in pin is asserted low, match out is ORed.
• Read Write Control Logic The Read Write Control logic governs write access to the Block-Ram
(BRAM80K) based on trigger detection. This mechanism, which operates in the user clock domain,
generates write addresses and control signals used to write captured user data to the BRAM. It also
generates read addresses and control signals after the user data gets written to BRAM. Read/Write
address counters are enabled by a read-write controller state machine.
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up to two, if the Stimuli output is being used
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