Setting the ip configuration, Generating the ip design files, Adding configuration files to a project – Achronix ACE Version 5.0 User Manual
Page 272: Generating, The ip design files
Creating an IP Configuration
Chapter 4. Tasks
Setting the IP Configuration
From the IP Editor, use either the
Back
and Next
or the
to navigate the editor pages, setting
the appropriate values needed for the desired configuration. Any errors and warnings are displayed in the
. Some IP Editors will also display supplemental graphical information in the
Calculated Fields
Some of the fields in the
, and
pages are never editable. These fields contain calculated values based upon the current contents of
user-editable fields. These calculated fields are provided for informational purposes.
Many of these calculated values have limited ranges of legal values - when the calculated value falls outside
the legal range, the calculated values background color will change to indicate a problem. Just like when
user-editable IP configuration properties fall outside a legal range, an IP Problem entry (see
) is created. But an IP Problem created by a calculated value field will not ”blame” the calculated value
field, it will instead blame one of the user-editable properties involved in its calculation. While only one field
is blamed in an IP Problem entry, be aware that all active fields that might be involved in the calculation are
listed in the IP Problem entry as potential fields which, when changed, might fix the IP Problem.
For example, when one of the PLL’s four ”clkout Output Frequency” calculated values is outside its legal
range, it blames the user-editable ”Refclk Input Frequency (MHz)”. While the ”Refclk Input Frequency
(MHz)” is just one of the user-editable fields involved in the calculation (there are over a dozen other user-
editable fields potentially involved), it is always relevant, and the cyclic nature of the circuit, particularly
when in external feedback mode, makes it impossible to pick a single most-relevant user-editable field.
IP Editor Navigation
The user may navigate between sequential IP Editor pages by using the
Back
and Next
buttons. When
one of these buttons becomes disabled, it means there are no further pages of configuration information in
the indicated direction.
The currently active page is always selected in the
. The user may navigate directly to a given
IP Configuration Page simply by selecting the desired page name in the
The user may left-click on any text in the
to turn to the IP Configuration Editor page
containing the settings for that text.
The user may double-click a table entry in the
to turn to the IP Configuration Editor page
containing the property being blamed for the selected IP Problem.
Generating the IP Design Files
After setting the IP configuration, click the Generate IP Design Files icon (
) to open the
. Select the desired options such as whether to generate the Verilog wrapper, VHDL
wrapper, timing constraints, placement constraints, etc. After selecting the desired options and file paths,
click Finish to create the selected files.
Note:
The generated VHDL RTL wrapper is not standalone. It requires the generated Verilog
RTL file.
Adding Configuration Files to a Project
If the option Add to active project in the
box was not selected, the
configuration files must be manually added to the active project. Use the procedure under
to add the configuration file and its related source files to the active project.
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