Set_default_relation, Set_extra_delay, 142set default relation – Achronix ACE Version 5.0 User Manual

Page 374: 143set extra delay, Set default relation, Set extra delay

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set extra delay

Chapter 5. Tcl Command Reference

[-wt

<

arg

>

]

Optional

Optional 2nd level cluster weight
2, . . . , 5 - higher weights signify
cluster importance

This clustering command directs the placer to keep the instances (listed in the command) together. For loops
and long paths of reconvergent paths, the tool knows to focus on placing these instances together, yielding
better results.

set default relation

set default relation [-none] [-false path] [-related]

Specify default when a needed clock relation is not specified.

Argument

Required/Optional

Description

[-none]

Optional

do not infer a relation (default)

[-false path]

Optional

assume set false path

[-related]

Optional

infer relation from period
specified with create clock;
otherwise false path

set extra delay

set extra delay

<

pinlist

>

This command parses the user directive to add extra gate delays for reconvergent (skewed) paths.

Argument

Required/Optional

Description

<

pinlist

>

Required

The required pinlist option is used to
specify the load pins of a net that need
to be driven by inserted gates. For each
pin, you can optionally specify an
integer delay value by using the format
<

delay>,<pin name>. The default

delay value is 1.

Elaboration

This command will insert delays using a structure specified by user directives that have been applied to the
design prior to

run prepare

.

1

s e t e x t r a d e l a y { < p i n l i s t > }

where

1

<

p i n l i s t > : = ’ { ’ pin1 pin2 pin3 . . . . ’ } ’

The lists are TCL lists of pins on the same net. Note that each pin in <pinlist> should be separated by a
space.
It is an error to specify a set of pins that are not on the same net.
It is not necessary to list all target pins of the net. All pins not specified are assumed to be at the first level.

Each level of the list corresponds to a ”buffer” to be inserted on the path to the pin. The buffer is
implemented by a LUT.

UG001 Rev. 5.0 - 5th December 2012

http://www.achronix.com

362

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