Achronix ACE Version 5.0 - Manual (Page 259)

Running the Flow Chapter 4. Tasks
Running the Flow
A flow can only be run on the current active implementation. If no active implementation is set in the
Projects view, then the flow steps in the Flow view are disabled. Some flow steps are optional while others
are required. Optional flow steps may be enabled or disabled in the flow by checking or un-checking the
checkbox to the left of each flow step label.
Running the Entire Flow
To sequentially run through all of the available flow steps in order:
1. Activate an implementation in the Projects view.
2. Click on the Run Flow toolbar button ( ) in the Flow view.
3. (Optionally) Stop the flow from continuing to the next flow step at any time by clicking the Stop Flow
toolbar button ( ) in the Flow view.
As each flow step is run, its status changes from incomplete to running to either error or complete. If an
error occurs during the execution of a flow step, the flow stops running any further steps. Disabled flow
steps are not executed during this operation.
Running a Sub-Flow
To run a subset of the available flow steps:
1. Activate an implementation in the Projects view.
2. Double-click on a flow step or flow category in the Flow view.
3. (Optionally) Stop the flow from continuing to the next flow step at any time by clicking the Stop Flow
toolbar button ( ) in the Flow view.
As each flow step is run, its status changes from incomplete or running to either error or complete. If an
error occurs during the execution of a flow step, the flow stops running any further steps. Disabled Flow
steps are not executed during this operation.
Note: Running a flow step out of order may result in an error.
Prepare Steps
Run Prepare
The first flow step required for any design is Run Prepare. This step (in order):
1. Clears all previously loaded netlists and constraints
2. Loads and compiles the device
3. Loads all the design files for the active implementation into ACE
4. Runs design checks
5. Transmutes the design into an Achronix design
The active project is saved to disk automatically when this step is successfully completed. In addition, this
step automatically generates a pin assignment and an utilization report.
Once the active implementation is prepared, the design is ready to be placed or analyzed for timing results.
An encrypted Verilog netlist can also be generated for the prepared implementation for simulation. I/O
pre-placement can also be done once the design is prepared (see
Pre-Placing a Design ).
247 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012