Achronix ACE Version 5.0 - Manual (Page 201)

Dialogs Chapter 3. Concepts
Generate IP Design Files Dialog
The Generate IP Design Files dialog is used to create the necessary RTL models, timing constraints and
bitstream files for configuring embedded IP. The files generated are based upon the configuration file
(
.acxip ) created via the active IP Configuration Editor . See also: Creating an IP Configuration .
Figure 3.103: Generate IP Design Files Dialog including supplemental SerDes fields
Generate IP Design Files Dialog Fields
Field Default Description
RTL Models
Verilog Model Selected Selects whether a Verilog model for the
configuration is generated.
(1)
VHDL Model Deselected Selects whether a VHDL model for the
configuration is generated.
(1)(2)
Timing Constraints
SDC Constraints Selected Selects whether an SDC constraints file for the
configuration is generated.
(1)
189 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012