Achronix ACE Version 5.0 User Manual
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Editors
Chapter 3. Concepts
DDR3 Editor Overview Page Options
Option
Description
Target Device
Allows the user to select from the Achronix devices that support this IP.
Placement
Select the location on the chip where this DDR interface should be placed.
Clock Pin
Name
Enter the reference clock pin name. Will be used to generate clock constraints. May be
a top level design pin, a PLL clock output pin, etc.
DIMM Type
Select from a predefined library of standard DIMMs, or select Custom for full
customization options.
Data Rate
(Mbps)
May be configured to use a standard rate, or may be customized.
Fabric Interface
Width
Wide fabric (core) interface widths running at half speed are needed to achieve the
highest speed Data Rate values.
Data Width
Local side data width.
Number of
CLKOUTs
Number of DDR3 DIMM clocks.
Number of
Ranks
Number of chip selects used.
Address
Command
Delay (hex)
The number of pipe stages in the address and command path.
Enable Address
Mirroring
Enable Address Mirroring in the DDR Controller.
Enable Wide
Bus Interface
When enabled, this doubles the width of the data bus, and helps meet timing at
higher frequencies.
DIMM Settings
Number of
Column Bits
Number of bits for Column Address.
Number of
Row Bits
Number of bits for Row Address.
Number of
Bank Bits
Number of bits for Bank Address.
DQ Per DQS
Number of DQ bits per DQS line.
Registered
DIMM
Whether or not the DDR3 DIMM is registered.
UG001 Rev. 5.0 - 5th December 2012
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