Achronix ACE Version 5.0 User Manual
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Editors
Chapter 3. Concepts
clkout0 Desired
Frequency
Y
The frequency desired for clkout0. ACE will automatically
choose PLL configuration values (NR, NF, OD0, OS0) to get as
close to the desired frequency as possible.
clkout0
Achieved
Frequency
The calculated output frequency of the clkout0 clock output
signal. This will be as close to the ”clkout0 Desired Frequency”
as possible.
VCO
Frequency
The calculated VCO output frequency which was required to
achieve the requested clkout0 frequency. This will also be used
to drive any other enabled clkout outputs.
Additional Clkout Outputs
clkout[1-3]
Desired
Divider
Y
The requested divider to use to alter the VCO Frequency for the
clkout output. Some values in the allowed range are not
achievable - in these cases, a warning is reported and the closest
divider is used instead. Changing this option value will change
the associated clkout Output Frequency.
clkout[1-3]
Output
Frequency
The achieved output frequency of the named output. This will
vary according to the VCO Frequency and the clkout Desired
Divider.
Placement
Site Corner
Y
The corner of the Speedster22i device where this PLL instance
should be placed. The four choices are NE, SE, SW, and NW.
Site Index
Y
The site index within the corner where this PLL instance should
be placed.
UG001 Rev. 5.0 - 5th December 2012
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