Achronix ACE Version 5.0 - Manual (Page 29)

Editors Chapter 3. Concepts
Output Synthesizer [0,1,2,3] Pages
The Output Synthesizer (OS) pages contain configuration information relating to the OS associated with
the PLLs selected clock output. Because the OS can be disabled for a PLL clock output, this page is only
visible when the ”Enable Output Synthesizer (OS[0-3])” field on the appropriate
Clock Output [0,1,2,3] Page
is enabled.
Figure 3.8: IP Advanced PLL Editor Output Synthesizer 0 Page
PLL Editor Output Synthesizer Page Options
Option Editable Description
OS[0-3] Input
Frequency
The calculated frequency of the OS input signal.
OS[0-3] Divider Y The factor by which the signal entering the OS should be
divided before it exits the OS. As this increases, the OS
output frequency decreases. (Unless this OS is in the
external feedback path, in which case increasing this value
does not affect the OS output frequency, but instead
increases the VCO output frequency.)
OS[0-3] Output
Frequency
The calculated frequency of the OS output signal.
17 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012