Achronix ACE Version 5.0 - Manual (Page 25)

Editors Chapter 3. Concepts
Clock Output [0,1,2,3] Pages
The Clock Output pages each contain general configuration information relating to a single PLL output
signal. Since there are one-to-four PLL output signals per PLL (as configured on the
Overview Page ),
between one and four Clock Output pages will be enabled.
Figure 3.5: IP Advanced PLL Editor Clock Output 0 Page
PLL Editor Clock Output Page Options
Option Editable Description
clkout Output
Frequency
The calculated frequency of this clock output signal as it
exits the PLL.
Bypass PLL and
Output Divider
(OD[0-3])
Y Enabling this will bypass the NR, PFD, VCO, and OD,
sending the reference clock input signal directly to the OS
input. Disabling this allows normal PLL behavior. Note that
when this is enabled, the IP Editor configuration page for
the Output Divider (OD) associated with this clock output is
disabled. In addition, when enabled, it becomes illegal to
use this output in an external feedback path, as the PLL will
lose lock.
Enable Output
Synthesizer
(OS[0-3])
Y Allows this clock output to use its Output Synthesizer (OS).
When enabled, this activates the IP Editor configuration
page for the OS associated with this clock output. When
disabled, the associated OS configuration page is hidden.
13 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012