Achronix ACE Version 5.0 - Manual (Page 99)

Editors Chapter 3. Concepts
Clock Enable
Priority
The Clock Enable Priority defines the priority of the outregce clock
enable input relative to the rstreg reset input during an assertion of the
rstreg signal on the read port output register. Setting this field to rstreg
allows the output register to be set/reset at the next active edge of the read
port clock without requiring a specific value on the
outregce output
register clock enable input. Setting this field to regce requires that the
outregce output register clock enable input is high for the output register
set/reset operation to occur at the next active edge of the read port clock.
Memory Initialization File Path to initialization file whose data is ”Data Width” wide and ”Address
Depth” deep. The memory initialization file should be in hexadecimal.
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