Achronix ACE Version 5.0 - Manual (Page 31)

Editors Chapter 3. Concepts
Advanced PLL Editor Port Names Page Options
Option Description
Input Ports
Name for Input ”refclk” The desired name for the reference clock input
signal in the generated RTL.
Name for Input ”fbclk” The desired name for the feedback clock input
signal in the generated RTL. This option is not
available when the PLL is in Pure Internal
Feedback Mode.
Phase inc[0-3] Input Port Name The desired name for the phase inc input signal
(for the appropriately numbered clock output) in
the generated RTL.
Output Ports
Clkout Output [0-3] Port Name The desired name for the PLL clock output in the
generated RTL.
Name for Output ”pll lock” The desired name for the PLL’s lock indication
output signal in the generated RTL.
19 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012