Achronix ACE Version 5.0 User Manual
Page 22
Editors
Chapter 3. Concepts
PLL Editor Overview Page Options
Option
Editable
Description
Target Device
Y
The Speedster22i device this PLL is intended to target.
Refclk Input
Frequency (MHz)
Y
The frequency of the PLL reference clock input.
Number of Desired
Clock Outputs
Y
The number of desired clock output signals for this PLL.
Changing this will alter the number of active pages of
Clock Output configuration options.
clkout Output
Frequency
The calculated output frequency of the named clock
output signal. The number of outputs listed will match
the ”Number of Desired Clock Outputs”.
Reference Divider
”NR”
Y
The amount by which the reference clock frequency
should be divided before entering the PLLs Phase
Frequency Detector. As this value increases, the ”VCO
Frequency” decreases.
Divided Reference
Frequency
The calculated reference clock frequency after having
been divided by the ”Reference Divider ’NR’”.
Feedback Mode
Y
Selects one of the three allowed feedback modes, and
enables/disables related options on this page according
to the selected mode. See Feedback Modes below for
more details.
Feedback Path Total
Divisor Product
The calculated total product of all divisors in the present
feedback path.
VCO Frequency
The calculated VCO output frequency. The algorithm
used will vary depending upon the selected Feedback
Mode.
Feedback Divider
”NF”
Y
The amount by which the feedback signal should be
divided before entering the PLLs Phase Frequency
Detector. As this value increases, the ”VCO Frequency”
increases. When in Pure Internal Feedback Mode, this
may be a floating-point value; in Mixed feedback mode
this must be an integer value. In Pure External Feedback
Mode, this option will be disabled.
Closest NF Fractional
Numerator
This calculated values represents the fractional portion of
the entered ”Feedback Value ’NF’” used to configure the
PLL. When floating point values are entered for the
”Feedback Divider ’NF’”, they must be represented as
fractions of 65536 (a 16-bit representation of the fraction is
used). The value displayed provides the closest possible
fraction to that requested by the user.
Difference between
target and achieved
This calculated value shows how close the PLL can come
to the requested ”Feedback Divider ’NF’” value. (Some
requested fractional values are impossible to exactly
represent within the 16 bits available in the PLL.)
UG001 Rev. 5.0 - 5th December 2012
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