Achronix ACE Version 5.0 User Manual
Page 80
Editors
Chapter 3. Concepts
Write Clock Polarity
Y
The write port clock polarity can be set to use
either rising edge assignment or falling edge
assignment.
Output Register Enabled
Y
When the Output Register is enabled, there is
an additional cycle of latency for each read
operation.
Output Register
Clock Enable Priority
Y
The Clock Enable Priority defines the priority
of the outregce clock enable input relative to
the rstreg reset input during an assertion of
the rstreg signal on the read port output
register. The value rstreg allows the Port A
output register to be set/reset at the next
active edge of the read port clock without
requiring a specific value on the outregce
output register clock enable input. The value
regce
requires that the outregce output
register clock enable input is high for the
output register set/reset operation to occur at
the next active edge of the read port clock.
Use Memory Initialization File
Y
Enable the use of a Memory Initialization File.
Memory Initialization
Memory Initialization File
Y
Path to initialization file whose data is ”Data
Width” wide and ”Address Depth” deep. The
memory initialization file should be in
hexadecimal.
Total Memory Size
Reports the total memory size for the
currently configuration, in bits.
Number of LRAMS Used
Reports the total number of LRAMs which
will be instantiated to support the current
configuration.
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