Achronix ACE Version 5.0 - Manual (Page 36)

Editors Chapter 3. Concepts
Overview Page
The Overview page contains all the properties that govern the structure and configuration of the BRAM
wrapper.
BRAM Editor Overview Page Options
Option Editable Description
Port A
Port A Configuration Y BRAMs can be configured for read, write, or
read/write capability independently on both
Port A and Port B sides of the BRAM.
Data Width Y Port A side write and read port data width.
We currently only support Port A data width
being a ratio of 1:2n or 2n:1 with Port B data
width. The max ratio is 1:32 or 32:1. This
field imposes limitations on the Port B side
data width and address depth.
Address Depth Y Port A side address depth is the total number
of data words accessible via Port A. This field
imposes limitations on the Port B side data
width and address depth. The Port B data
width must be a valid integer ratio of the
Port A data width.
Write Mode Y The write mode can be set to No Change in
order to keep the read port value constant
until the next read. It can be set to Write First
to allow the write data to be seen on the read
port before the next read.
Clock Polarity Y The write port clock polarity can be set to use
either rising edge assignment or falling edge
assignment.
Port Enable Active-High Y When this is enabled, the port enable pea is
active-high. Otherwise, the port enable will
be active-low.
Output Latch Reset Active-High Y When this is enabled, the output latch has an
active-high synchronous reset. Otherwise,
the output latch reset will be active-low.
Output Register Enabled Y When the Output Register is enabled, there is
an additional cycle of latency for each read
operation.
Output Register
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