Achronix ACE Version 5.0 - Manual (Page 239)

Projects Chapter 3. Concepts
Project File
Projects are persisted in project files ( .acxprj file extension) created automatically by the tool whenever a
project is saved. A project file is actually just a Tcl script supporting only a defined subset of Tcl commands.
Users can edit project files manually and then load them into the tool to use as a script or for running
regressions.
In the GUI, loaded project file contents are displayed in a tree structure in the Projects view . Project file
contents may also be viewed in a text editor in the GUI by double-clicking on the project name in the
Projects view (example file contents shown below):
=======================================================
# proj2
# AUTOMATICALLY GENERATED FILE
# MAY BE OVERWRITTEN AT ANY TIME DURING USE OF TOOL
# Netlist Files
add_project_netlist -project proj2 "C:/test_projects/proj2/top.vma"
# Constraint Files
add_project_constraints -project proj2 "C:/test_projects/proj2/clock_mode2.sdc"
add_project_constraints -project proj2 "C:/test_projects/proj2/clock_mode1.sdc"
# Implementations
# impl_1
create_impl -project proj2 impl_1
set_impl_option -project proj2 -impl impl_1 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_1 speed_grade "standard"
set_impl_option -project proj2 -impl impl_1 core_voltage "1.00"
enable_project_constraints -project proj2 -impl impl_1 "C:/test_projects/proj2/clock_mode2.sdc"
disable_project_constraints -project proj2 -impl impl_1 "C:/test_projects/proj2/clock_mode1.sdc"
# impl_2
create_impl -project proj2 impl_2
set_impl_option -project proj2 -impl impl_2 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_2 speed_grade "standard"
set_impl_option -project proj2 -impl impl_2 core_voltage "0.95"
enable_project_constraints -project proj2 -impl impl_2 "C:/test_projects/proj2/clock_mode2.sdc"
enable_project_constraints -project proj2 -impl impl_2 "C:/test_projects/proj2/clock_mode1.sdc"
# impl_3
create_impl -project proj2 impl_3
set_impl_option -project proj2 -impl impl_3 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_3 speed_grade "standard"
set_impl_option -project proj2 -impl impl_3 core_voltage "0.95"
disable_project_constraints -project proj2 -impl impl_3 "C:/test_projects/proj2/clock_mode2.sdc"
disable_project_constraints -project proj2 -impl impl_3 "C:/test_projects/proj2/clock_mode1.sdc"
# End of file
=======================================================
Source Files
A project contains source files used as inputs to the ACE flow. There are two types of source files:
• Synthesized netlist files
• SDC/PDC constraints files
In the GUI, source files may be browsed in the Projects view and viewed in the built-in text editor by double
clicking on the file name in the Projects view .
IP Configurations
ACE provides GUI support to ease configuration of the most complicated embedded IP in Achronix FPGAs.
The data files used by the
IP Configuration Editors (files with the .acxip extension) may optionally be
227 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012