Achronix ACE Version 5.0 User Manual

Page 98

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Editors

Chapter 3. Concepts

Overview Page

The Overview page contains all the properties that govern the structure and configuration of the ROM
wrapper.

Figure 3.48: ROM IP Editor Overview Page

ROM Editor Overview Page Options

Option

Description

RAM Type

The ROM can be built out of Block RAMs or Logic RAMs.

Data Width

Data width of the read port.

Address Depth

Desired address depth of the ROM.

Read Clock Polarity

The read port clock polarity can be set to use either rising edge assignment
or falling edge assignment.

Output Register Enabled

When the Output Register is enabled, there is an additional cycle of latency
for each read operation.

Output Register

UG001 Rev. 5.0 - 5th December 2012

http://www.achronix.com

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