Achronix ACE Version 5.0 User Manual
Page 202
Dialogs
Chapter 3. Concepts
Placement Constraints
Selected
Selects whether a placement constraints file for the
configuration is generated.
(1)
Additional Generate IP Design Files Dialog Fields (SerDes-only)
Field
Default
Description
Bitstream Configuration
Quad 0 Bitstream
Config
Selected
Selects whether a bitstream file for Quad 0 for the
configuration is generated.
(1)(3)
Quad 1 Bitstream
Config
Selected
Selects whether a bitstream file for Quad 1 for the
configuration is generated.
(1)(3)
Quad 2 Bitstream
Config
Selected
Selects whether a bitstream file for Quad 2 for the
configuration is generated.
(1)(3)
Quad 3 Bitstream
Config
Selected
Selects whether a bitstream file for Quad 3 for the
configuration is generated.
(1)(3)
Quad 4 Bitstream
Config
Selected
Selects whether a bitstream file for Quad 4 for the
configuration is generated.
(1)(3)
Notes:
(1)
The default file path is displayed below the option. An alternate path can be selected via the Browse
button.
(2)
The VHDL RTL Model is a simple wrapper around the Verilog RTL Model. Because of this, when using
the VHDL RTL Model, the Verilog RTL Model must also be generated and included in the user’s design.
(3)
This option is only available if needed by the configuration.
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