Achronix ACE Version 5.0 - Manual (Page 271)

Creating an IP Configuration Chapter 4. Tasks
Creating an IP Configuration
Achronix FPGAs feature embedded IP to support clock signal generation (PLLs), FIFOs, DDR3, Ethernet,
PCIe, and high-speed serial communication (SerDes). These highly flexible IP blocks require configuration
for proper operation.
ACE includes a number of IP Editors and Views which guide the user through the process of correctly
configuring IP. The data for these IP configuration editing sessions is stored in .acxip files, which may be
saved and loaded for future reuse or modification.
Using the data stored in the .acxip files, ACE will generate RTL wrappers (Verilog and VHDL 7 ) containing
the specified configuration parameters around the appropriate Achronix macro cells, as well as appropriate
.sdc and .pdc files to complete the IP timing and pre-placement configuration. These generated files may
then be incorporated into the user’s design for synthesis and simulation.
Creating and editing IP configurations is typically performed from the IP Configuration perspective ( ).
In addition to the IP Configuration editors, this perspective incorporates views allowing the user to:
• Create new IP configurations ( IP Libraries view )
• View a graphical diagram of the IP Configuration currently being edited ( IP Diagram view ); the
diagram may show the macro’s interface, the dataflow, and/or the placement of the IP instance within
the chip.
• Navigate instantly to any page of the active IP Configuration Editor, while displaying the names and
validity of each page ( Outline view )
• View a detailed list of all the errors and warnings pertaining to all IP Configuration files currently
opened ( IP Problems view ). This view also allows the user to navigate directly to the source of the
problem in the relevant IP Configuration Editor.
See also: Advanced PLL Configuration Editor , Basic PLL Configuration Editor , DDR3 Configuration Editor ,
Ethernet Configuration Editor , FIFO Configuration Editor , PCI Express (PCIe) Configuration Editor , and
Serdes Configuration Editor .
Creating and Naming an IP Configuration
Switch to the IP Configuration perspective either by clicking the IP Configuration perspective icon ( )
or selecting Open Perspective → IP Configuration from the main menu. Select File → New → IP
Configuration. . . from the main menu, or use the IP Libraries view (see IP Libraries View ) to open the
New IP Configuration dialog dialog. After setting the location and name for the configuration file, click
Finish to complete the process and activate the appropriate IP Editor.
7 use of a generated VHDL wrapper also requires the generated Verilog wrapper
259 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012