Achronix ACE Version 5.0 - Manual (Page 30)

Editors Chapter 3. Concepts
Port Names Page
The Port Names page contains all the input and output ports which will be used by the PLL in its current
configuration. (Changing options on other pages will show and hide port names on this page, as the need
for the ports changes.)
Figure 3.9: IP Advanced PLL Editor Port Names Page
NOTE: All port names entered on this page must adhere to Verilog and VHDL naming
standards. Illegal names will be caught as errors, and will prohibit RTL wrapper file
generation.
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