Achronix ACE Version 5.0 - Manual (Page 378)

set input transition Chapter 5. Tcl Command Reference
set input delay
set input delay delay port pin list [-clock < arg > ] [-combinational]
Specify an input delay constraint or clock
Argument Required/Optional Description
delay Required delay value (Note: this value is currently ignored)
port pin list Required port pin list (one or more ports)
[-clock < arg > ] Optional clock name
[-combinational] Optional use combinational domain
Elaboration
This command specifies an input delay constraint or clock using a structure specified by user directives that
have been applied to the design prior to run prepare.
For example user wants to use an input pin as a combinational pin, which is not registered input; below is
the example how to set the input delay inside the SDC file:
set_input_delay 0 <port_pin_list> -combinational
If the user design has input pins defined as bus. Then in this case user needs to split the bus into a bit and
use the following constraint inside the SDC file:
set_input_delay 0 {<port_pin_list[bit_value_of_bus]>} -combinational
or in easier way user can use for loop in SDC file
for {set i 0} {$i < <bus_width>} {incr i} {
set_input_delay 0 <port_pin_list\[$i\]> -combinational
}
For example in user design an input pins (abus [18:0]) are defined as 19-bit bus. Instead of using 19-line
with bit-split user can use this above sample. Below is the example how to define 19-bit bus inside the SDC
file:
for {set i 0} ($i < 19) {incr i} {
set_input_delay 0 abus\[$i\] -combinational
}
User can also set the constraint on the input pin with respect to clock. Below is the example how to do this
in the SDC constraint file
set_input_delay 0 <port_pin_list> -clock <clock_name>
or [If the input pins are bus]
set_input_delay 0 {<port_pin_list[bit_value_of_bus]>} -clock <clock_name>
But it is recommended for the user to register the input pins with respect to design clock instead of using
the above constraint file.
set input transition
set input transition slew port pin list
Specify an input slew/transition constraint
UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.com 366