Achronix ACE Version 5.0 User Manual
Page 56
Editors
Chapter 3. Concepts
Overview Page
The Overview page contains the top-level, global properties that govern the structure and base
configuration of the FIFO.
FIFO Editor Overview Page Options
Option
Editable
Description
Clock Mode
Y
FIFOs can be configured in Single Clock mode to
use a single clock domain for writes and reads.
Single clock mode bypasses the synchronization
circuitry to enable faster updates to status flags.
Dual Clock mode allows two independent clocks
to be used for reads and writes.
Write Data Width
Y
The FIFO write data width.
Write Address Depth
Y
The FIFO address depth is the total number of
writable data words in the FIFO.
Read Data Width
Y
The FIFO read data width.
Read Address Depth
The total number of readable data words in the
FIFO.
Total Memory Size
The total memory size in bits.
Number of BRAMs Used
The number of BRAMs used in the configuration.
First Word Fall Through
Enabled
Y
When enabled, the first value written into the FIFO
appears at the dout output without having to
perform a read operation. If First Word Fall
Through is disabled, the first data word written
into the FIFO is available at the FIFO output one
rdclk clock cycle after the first read operation. This
parameter only affects the availability of the first
word written into the FIFO after an empty
condition. Operation of the two modes is the same
after the first read operation is performed.
Output Register Enabled
Y
When the Output Register is enabled, there is an
additional cycle of latency for each read operation.
The Output Register is always enabled in Dual
Clock mode.
Output Register
Reset Active High
Y
When this is enabled, the output register has an
active-high synchronous reset. Otherwise, the
output register reset will be active-low.
UG001 Rev. 5.0 - 5th December 2012
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