Fpga programming steps, Running multiple flows in parallel – Achronix ACE Version 5.0 User Manual
Page 261
Running the Flow
Chapter 4. Tasks
final simulation netlist can be generated without errors. If your design fails final DRC checks, you can still
generate a Post-Route timing report for experimental purposes. However, no bitstream may be generated
to run the design on the hardware unless all final DRC checks pass.
Run Sign-off Timing Analysis (Optional)
After Run Final DRC Checks has successfully completed on an implementation, the Run Sign-Off Timing
Analysis
step can be run. This step generates and writes a final sign-off timing report file for the placed and
routed design, after all final DRC checks have passed. The generated report is automatically displayed in
the editor area upon successful completion. This step is run by default when Run Flow is executed.
Generate Final Simulation Netlist (Optional)
After Run Final DRC Checks has successfully completed on an implementation, the Generate Final
Simulation Netlist
step can be run. This step generates and writes an encrypted, post-place-and-route
Verilog simulation netlist file from the final DRC-free design. This netlist may be used to simulate the post-
place-and-route design. This step is not run by default when Run Flow is executed.
FPGA Programming Steps
Generate Bit Stream
After a design is placed and routed, a bitstream for the target device can be generated. This step generates
a bitstream (STAPL file) for the current implementation based on the settings in the
(see the
Options settings for Bitstream Generation). This step is run by default when Run Flow is executed.
FPGA Download
After the bitstream is generated, it is ready for downloading to the FPGA via the Bitporter pod specified
under the Options view settings (see the Options settings for FPGA Download). This step is not run by
default when Run Flow is executed.
A bitstream can also be downloaded to the FPGA via the
(see
For more details, refer to the Bitporter User Guide (UG004).
Running Multiple Flows in Parallel
Normally, ACE only allows a single
to be run through the
at a time.
Using the
, ACE allows users to run multiple implementations within a single project
through the flow in parallel, via a configurable number of parallel processes.
Executing multiple
implementations in this manner allows ACE to provide a
of the resulting
frequencies
1
, permitting the user to make QOR performance comparisons between implementations
utilizing different starting clock constraints, placement constraints, and potential optimizations.
Finding the Multiprocess View
To make use of the Multiprocess View, it must first be made visible. (It is hidden by default.) To show
the Multiprocess View, first select the
(
). Then, in the
, select the Show
Multiprocess View
(
) button. This will cause the Multiprocess view to be displayed, and will also
hide/minimize the ACE Editor Area (where reports are displayed) to allow sufficient screen area for the
Multiprocess view. (The next time an ACE report is generated/opened, the ACE Editor Area will again
become visible.)
Alternately, the Multiprocess view may be displayed without side-effects from within any perspective by
selecting Window → Show View → Other. . . → Achronix → Multiprocess.
1
if the optional Post-Route Timing Analysis or Sign-off Timing Analysis
are enabled
249
UG001 Rev. 5.0 - 5th December 2012