Achronix ACE Version 5.0 - Manual (Page 297)

Running the SnapShot Debugger Chapter 4. Tasks
Figure 4.18: SnapShot Trigger Detector Block Diagram
• Trace Buffers Trace Buffers are implemented using 2048×36 Block-RAMs (BRAM80K). The Block-
RAMs (BRAM80K) are used to capture user data with respect to the user clock, and in turn this
data can be read serially through the JTAG. The number of BRAMs used will vary based upon the
data width selected by the user. The combined BRAMs have an aggregate dimension of 2048 x
MNTR WIDTH, which allows capturing up to 2048 samples at the user logic clock rate in real-time.
Counters generate Read/Write addresses for the BRAM, while control signals are generated by the
Read/Write controller.
Using the SnapShot Macro
The SnapShot macro ACX SNAP SHOT exists inside the Speedster Black-Box library file
( speedster22i user macro io.v ). The ACX SNAP SHOT macro must be synthesized
together with the user design (instantiation example shown below). The user must include the
speedster user macro io.v file during synthesis while implementing the SnapShot macro.
Two clocks are present inside the SnapShot macro. These two clocks are
1. tck : This clock is used to read the data-out from SnapShot macro through the JTAG tdo port. It is an
IEEE 1149.1 JTAG based TCK.
2. usr clk : This clock is used for the user data into the SnapShot macro and the non-JTAG macro outputs
The usr clk must match the desired clock frequency of the user’s design. An example is provided below
showing how to implement the SnapShot macro inside the user’s design.
Macro Interface
SnapShot Macro Pin Descriptions
Pin
Name
Type
Clock
Domain
Description
tck 1) Input tck JTAG Test Clock
trstn 1) Input tck JTAG Test Reset (active low)
tdi 1) Input tck JTAG Test Data In
tms 1) Input tck JTAG Test Mode Select
tdo 1) Output tck JTAG Test Data Out
usr clk 1) Input usr clk User Logic clock (same as Users Design clock value)
trigger ch
[35:0]
Input usr clk 36-bit Trigger Channel Data. This must correspond with
Monitor ch [35:0].
Monitor ch
[MNTR WIDTH -
1:0]
Input usr clk 36-144 bit tapped user logic data bus. Monitor ch [35:0] must be
equivalent to trigger ch [35:0].
285 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012