Achronix ACE Version 5.0 User Manual
Page 93
Editors
Chapter 3. Concepts
Phantom Functions
Support
Phantom Function support for the Function must be enabled by the Phantom
Functions Enable field in the Device Control register before the Function is
permitted to use the Function Number field in the Requester ID for Phantom
Functions. If Phantom Functions Supported != 00, the core implements the
Phantom Functions Enable register as read/write resetting to 0 and otherwise
implements Phantom Functions Enable as read only tied to 0.
Completion Timeout
Disable Supported
Set to signal that user Completion Timeout mechanism supports being
disabled; clear to indicate that the user Completion Timeout mechanism may
not be disabled. Setting this bit is required by PCIe Spec. for Endpoints which
issue requests on their own behalf so 1 is the recommended value.
Completion Timeout
Range
The supported completion timeout range. Devices are not required to support
several timeout ranges. 50uS to 50mS is the recommended value.
Enable AER Version
0x2
1 == Implement AER to version 0x2 (PCIe 2.1 and later Specification revisions).
Correctable Errors: Corrected Internal Error & Header Log Overflow are
enabled. Uncorrectable Error: Uncorrected Internal Error is enabled. 0 ==
Implement AER to version 0x1 (PCIe 2.0 and earlier Specification revisions).
Correctable Errors: Corrected Internal Error & Header Log Overflow are
hidden and cannot be signaled. Uncorrectable Error: Uncorrected Internal
Error is hidden and cannot be signaled.
Disable MSI
Capability
When disabled, the core’s MSI Capability is removed from the Configuration
Registers Capabilities List, MSI Interrupt functionality is disabled, and it will
not be possible to send MSI interrupts
Number of MSI
Vectors
Multiple message MSI functionality requires the user design to indicate the
interrupt vector number that they want signaled when mgmt interrupt is
asserted. MSI Multiple Message Capable advertises the desired number of
vectors. System software is not required to provide the desired number of
vectors and programs the allocated number of vectors into the Multiple
Message Enable configuration register.
Disable MSI-X
Capability
When disabled, the core’s MSI-X Capability is removed from the
Configuration Registers Capabilities List, MSI-X Interrupt functionality is
disabled, and it will not be possible to send MSI-X interrupts; this bit only
affects core configurations that support MSI-X
Number of MSI-X
Table Entries
MSI-X functionality requires the user design to implement the MSI-X Table in
Memory Space. MSI-X Table Size[10:0] is set to indicate the number of MSI-X
Table entries (Interrupt Vectors) implemented. MSI-X Table Size is read by
software to determine the size of the MSI-X Table.
MSI-X Table BAR
Indicator
MSI-X functionality requires the user design to implement the MSI-X Table in
Memory Space mapped by 1 (32-bit) or 2 (64-bit) Memory Base Address
Registers. MSI-X Table BIR and MSI-X Table Offset indicate to system software
where the MSI-X Table is located.
MSI-X Table Offset
(hex)
Value to place into MSI-X Capability : Table Offset field. MSI-X Table BIR
indicates which Base Address Register contains the MSI-X Table
MSI-X PBA BAR
Indicator
Same as MSI-X Table BIR, but indicates the Base Address Register of the MSI-X
PBA rather than the MSI-X Table
81
UG001 Rev. 5.0 - 5th December 2012