Document Outline

• Cortex-R4 and Cortex-R4F Technical Reference Manual
• Contents
• List of Tables
• List of Figures
• Preface
  • About this book
    • Product revision status
    • Intended audience
    • Using this book
    • Conventions
    • Further reading
  • Feedback
    • Feedback on this product
    • Feedback on this book
• Introduction
  • 1.1 About the processor
  • 1.2 About the architecture
  • 1.3 Components of the processor
    • 1.3.1 Data Processing Unit
    • 1.3.2 Load/store unit
    • 1.3.3 Prefetch unit
    • 1.3.4 L1 memory system
    • 1.3.5 L2 AXI interfaces
    • 1.3.6 Debug
    • 1.3.7 System control coprocessor
    • 1.3.8 Interrupt handling
  • 1.4 External interfaces of the processor
    • 1.4.1 APB Debug interface
    • 1.4.2 ETM interface
    • 1.4.3 Test interface
  • 1.5 Power management
  • 1.6 Configurable options
  • 1.7 Execution pipeline stages
  • 1.8 Redundant core comparison
  • 1.9 Test features
  • 1.10 Product documentation, design flow, and architecture
    • 1.10.1 Documentation
    • 1.10.2 Design flow
    • 1.10.3 Architectural information
  • 1.11 Product revision information
    • 1.11.1 Processor identification
    • 1.11.2 Architectural information
• Programmer’s Model
  • 2.1 About the programmer’s model
  • 2.2 Instruction set states
    • 2.2.1 Switching state
    • 2.2.2 Interworking ARM and Thumb state
  • 2.3 Operating modes
  • 2.4 Data types
  • 2.5 Memory formats
    • 2.5.1 Byte-invariant big-endian format
    • 2.5.2 Little-endian format
  • 2.6 Registers
    • 2.6.1 The register set
  • 2.7 Program status registers
    • 2.7.1 The N, Z, C, and V bits
    • 2.7.2 The Q bit
    • 2.7.3 The IT bits
    • 2.7.4 The J bit
    • 2.7.5 The DNM bits
    • 2.7.6 The GE bits
    • 2.7.7 The E bit
    • 2.7.8 The A bit
    • 2.7.9 The I and F bits
    • 2.7.10 The T bit
    • 2.7.11 The M bits
    • 2.7.12 Modification of PSR bits by MSR instructions
  • 2.8 Exceptions
    • 2.8.1 Exception entry and exit summary
    • 2.8.2 Reset
    • 2.8.3 Interrupts
    • 2.8.4 Aborts
    • 2.8.5 Supervisor call instruction
    • 2.8.6 Undefined instruction
    • 2.8.7 Breakpoint instruction
    • 2.8.8 Exception vectors
  • 2.9 Acceleration of execution environments
  • 2.10 Unaligned and mixed-endian data access support
  • 2.11 Big-endian instruction support
• Processor Initialization, Resets, and Clocking
  • 3.1 Initialization
    • 3.1.1 MPU
    • 3.1.2 CRS
    • 3.1.3 FPU
    • 3.1.4 Caches
    • 3.1.5 TCM
  • 3.2 Resets
  • 3.3 Reset modes
    • 3.3.1 Power-on reset
    • 3.3.2 Processor reset
    • 3.3.3 Normal operation
    • 3.3.4 Halt operation
  • 3.4 Clocking
    • 3.4.1 AXI interface clocking
    • 3.4.2 Clock gating
• System Control Coprocessor
  • 4.1 About the system control coprocessor
    • 4.1.1 System control coprocessor functional groups
    • 4.1.2 System control and configuration
    • 4.1.3 MPU control and configuration
    • 4.1.4 Cache control and configuration
    • 4.1.5 TCM control and configuration
    • 4.1.6 System performance monitor
    • 4.1.7 System validation
  • 4.2 System control coprocessor registers
    • 4.2.1 Register allocation
    • 4.2.2 c0, Main ID Register
    • 4.2.3 c0, Cache Type Register
    • 4.2.4 c0, TCM Type Register
    • 4.2.5 c0, MPU Type Register
    • 4.2.6 c0, Multiprocessor ID Register
    • 4.2.7 The Processor Feature Registers
    • 4.2.8 c0, Debug Feature Register 0
    • 4.2.9 c0, Auxiliary Feature Register 0
    • 4.2.10 Memory Model Feature Registers
    • 4.2.11 Instruction Set Attributes Registers
    • 4.2.12 c0, Current Cache Size Identification Register
    • 4.2.13 c0, Current Cache Level ID Register
    • 4.2.14 c0, Cache Size Selection Register
    • 4.2.15 c1, System Control Register
    • 4.2.16 Auxiliary Control Registers
    • 4.2.17 c1, Coprocessor Access Register
    • 4.2.18 Fault Status and Address Registers
    • 4.2.19 c6, MPU memory region programming registers
    • 4.2.20 Cache operations
    • 4.2.21 c9, BTCM Region Register
    • 4.2.22 c9, ATCM Region Register
    • 4.2.23 c9, TCM Selection Register
    • 4.2.24 c11, Slave Port Control Register
    • 4.2.25 c13, FCSE PID Register
    • 4.2.26 c13, Context ID Register
    • 4.2.27 c13, Thread and Process ID Registers
    • 4.2.28 Validation Registers
    • 4.2.29 Correctable Fault Location Register
    • 4.2.30 Build Options Registers
• Prefetch Unit
  • 5.1 About the prefetch unit
  • 5.2 Branch prediction
    • 5.2.1 Disabling program flow prediction
    • 5.2.2 Branch predictor
    • 5.2.3 Incorrect predictions and correction
  • 5.3 Return stack
• Events and Performance Monitor
  • 6.1 About the events
  • 6.2 About the PMU
  • 6.3 Performance monitoring registers
    • 6.3.1 c9, Performance Monitor Control Register
    • 6.3.2 c9, Count Enable Set Register
    • 6.3.3 c9, Count Enable Clear Register
    • 6.3.4 c9, Overflow Flag Status Register
    • 6.3.5 c9, Software Increment Register
    • 6.3.6 c9, Performance Counter Selection Register
    • 6.3.7 c9, Cycle Count Register
    • 6.3.8 c9, Event Selection Register
    • 6.3.9 c9, Performance Monitor Count Registers
    • 6.3.10 c9, User Enable Register
    • 6.3.11 c9, Interrupt Enable Set Register
    • 6.3.12 c9, Interrupt Enable Clear Register
  • 6.4 Event bus interface
    • 6.4.1 Use of the event bus and counters
• Memory Protection Unit
  • 7.1 About the MPU
    • 7.1.1 Memory regions
    • 7.1.2 Overlapping regions
    • 7.1.3 Background regions
    • 7.1.4 TCM regions
  • 7.2 Memory types
    • 7.2.1 Using memory types
  • 7.3 Region attributes
    • 7.3.1 Cacheable memory policies
  • 7.4 MPU interaction with memory system
  • 7.5 MPU faults
    • 7.5.1 Background fault
    • 7.5.2 Permission fault
    • 7.5.3 Alignment fault
  • 7.6 MPU software-accessible registers
• Level One Memory System
  • 8.1 About the L1 memory system
  • 8.2 About the error detection and correction schemes
    • 8.2.1 Parity
    • 8.2.2 Error checking and correction
    • 8.2.3 Read-Modify-Write
    • 8.2.4 Hard errors
    • 8.2.5 Error correction
  • 8.3 Fault handling
    • 8.3.1 Faults
    • 8.3.2 Fault status information
    • 8.3.3 Correctable Fault Location Register
    • 8.3.4 Usage models
  • 8.4 About the TCMs
    • 8.4.1 TCM attributes and permissions
    • 8.4.2 ATCM and BTCM configuration
    • 8.4.3 TCM internal error detection and correction
    • 8.4.4 TCM arbitration
    • 8.4.5 TCM initialization
    • 8.4.6 TCM port protocol
    • 8.4.7 External TCM errors
    • 8.4.8 AXI slave interfaces for TCMs
  • 8.5 About the caches
    • 8.5.1 Store buffer
    • 8.5.2 Cache maintenance operations
    • 8.5.3 Cache error detection and correction
    • 8.5.4 Cache RAM organization
    • 8.5.5 Cache interaction with memory system
  • 8.6 Internal exclusive monitor
  • 8.7 Memory types and L1 memory system behavior
  • 8.8 Error detection events
    • 8.8.1 TCM error events
    • 8.8.2 Instruction-cache error events
    • 8.8.3 Data-cache error events
    • 8.8.4 Events and the CFLR
• Level Two Interface
  • 9.1 About the L2 interface
  • 9.2 AXI master interface
    • 9.2.1 Identifiers for AXI bus accesses
    • 9.2.2 Write response
    • 9.2.3 Linefill buffers and the AXI master interface
    • 9.2.4 Eviction buffer
    • 9.2.5 Memory attributes
  • 9.3 AXI master interface transfers
    • 9.3.1 Restrictions on AXI transfers
    • 9.3.2 Strongly Ordered and Device transactions
    • 9.3.3 Linefills
    • 9.3.4 Cache line write-back (eviction)
    • 9.3.5 Non-cacheable reads
    • 9.3.6 Non-cacheable or write-through writes
    • 9.3.7 AXI transaction splitting
    • 9.3.8 Normal write merging
  • 9.4 AXI slave interface
    • 9.4.1 AXI slave interface for cache RAMs
    • 9.4.2 TCM parity and ECC support
    • 9.4.3 External TCM errors
    • 9.4.4 Cache parity and ECC support
    • 9.4.5 AXI slave control
    • 9.4.6 AXI slave characteristics
  • 9.5 Enabling or disabling AXI slave accesses
  • 9.6 Accessing RAMs using the AXI slave interface
    • 9.6.1 TCM RAM access
    • 9.6.2 Cache RAM access
• Power Control
  • 10.1 About power control
  • 10.2 Power management
    • 10.2.1 Run mode
    • 10.2.2 Standby mode
    • 10.2.3 Dormant mode
    • 10.2.4 Shutdown mode
    • 10.2.5 Communication to the Power Management Controller
• Debug
  • 11.1 Debug systems
    • 11.1.1 Debug host
    • 11.1.2 Protocol converter
    • 11.1.3 Debug target
  • 11.2 About the debug unit
    • 11.2.1 Halting debug-mode debugging
    • 11.2.2 Monitor debug-mode debugging
    • 11.2.3 Programming the debug unit
  • 11.3 Debug register interface
    • 11.3.1 Coprocessor registers
    • 11.3.2 CP14 access permissions
    • 11.3.3 Coprocessor registers summary
    • 11.3.4 Memory-mapped registers
    • 11.3.5 Memory addresses for breakpoints and watchpoints
    • 11.3.6 Power domains
    • 11.3.7 Effects of resets on debug registers
    • 11.3.8 APB port access permissions
  • 11.4 Debug register descriptions
    • 11.4.1 Accessing debug registers
    • 11.4.2 CP14 c0, Debug ID Register
    • 11.4.3 CP14 c0, Debug ROM Address Register
    • 11.4.4 CP14 c0, Debug Self Address Offset Register
    • 11.4.5 CP14 c1, Debug Status and Control Register
    • 11.4.6 Data Transfer Register
    • 11.4.7 Watchpoint Fault Address Register
    • 11.4.8 Vector Catch Register
    • 11.4.9 Debug State Cache Control Register
    • 11.4.10 Instruction Transfer Register
    • 11.4.11 Debug Run Control Register
    • 11.4.12 Breakpoint Value Registers
    • 11.4.13 Breakpoint Control Registers
    • 11.4.14 Watchpoint Value Registers
    • 11.4.15 Watchpoint Control Registers
    • 11.4.16 Operating System Lock Status Register
    • 11.4.17 Authentication Status Register
    • 11.4.18 Device Power-down and Reset Control Register
    • 11.4.19 Device Power-down and Reset Status Register
  • 11.5 Management registers
    • 11.5.1 Processor ID Registers
    • 11.5.2 Claim Registers
    • 11.5.3 Lock Access Register
    • 11.5.4 Lock Status Register
    • 11.5.5 Device Type Register
    • 11.5.6 Debug Identification Registers
  • 11.6 Debug events
    • 11.6.1 Software debug event
    • 11.6.2 Halting debug event
    • 11.6.3 Behavior of the processor on debug events
    • 11.6.4 Debug event priority
    • 11.6.5 Watchpoint debug events
  • 11.7 Debug exception
    • 11.7.1 Effect of debug exceptions on CP15 registers and WFAR
    • 11.7.2 Avoiding unrecoverable states
  • 11.8 Debug state
    • 11.8.1 Entering debug state
    • 11.8.2 Behavior of the PC and CPSR in debug state
    • 11.8.3 Executing instructions in debug state
    • 11.8.4 Writing to the CPSR in debug state
    • 11.8.5 Privilege
    • 11.8.6 Accessing registers and memory
    • 11.8.7 Coprocessor instructions
    • 11.8.8 Effect of debug state on non-invasive debug
    • 11.8.9 Effects of debug events on processor registers
    • 11.8.10 Exceptions in debug state
    • 11.8.11 Leaving debug state
  • 11.9 Cache debug
    • 11.9.1 Cache pollution in debug state
    • 11.9.2 Cache coherency in debug state
    • 11.9.3 Cache usage profiling
  • 11.10 External debug interface
    • 11.10.1 APB signals
    • 11.10.2 Miscellaneous debug signals
    • 11.10.3 Authentication signals
  • 11.11 Using the debug functionality
    • 11.11.1 Debug communications channel
    • 11.11.2 Programming breakpoints and watchpoints
    • 11.11.3 Single-stepping
    • 11.11.4 Debug state entry
    • 11.11.5 Debug state exit
    • 11.11.6 Accessing registers and memory in debug state
  • 11.12 Debugging systems with energy management capabilities
    • 11.12.1 Emulating power down
• FPU Programmer’s Model
  • 12.1 About the FPU programmer’s model
    • 12.1.1 FPU functionality
    • 12.1.2 About the VFPv3-D16 architecture
  • 12.2 General-purpose registers
    • 12.2.1 FPU views of the register bank
  • 12.3 System registers
    • 12.3.1 Floating-Point System ID Register, FPSID
    • 12.3.2 Floating-Point Status and Control Register, FPSCR
    • 12.3.3 Floating-Point Exception Register, FPEXC
    • 12.3.4 Media and VFP Feature Registers, MVFR0 and MVFR1
  • 12.4 Modes of operation
    • 12.4.1 Full-compliance mode
    • 12.4.2 Flush-to-zero mode
    • 12.4.3 Default NaN mode
  • 12.5 Compliance with the IEEE 754 standard
    • 12.5.1 Complete implementation of the IEEE 754 standard
    • 12.5.2 IEEE 754 standard implementation choices
    • 12.5.3 Exceptions
• Integration Test Registers
  • 13.1 About Integration Test Registers
  • 13.2 Programming and reading Integration Test Registers
    • 13.2.1 Software access using APB
  • 13.3 Summary of the processor registers used for integration testing
  • 13.4 Processor integration testing
    • 13.4.1 Using the Integration Test Registers
    • 13.4.2 Performing integration testing
    • 13.4.3 ITETMIF Register (ETM interface)
    • 13.4.4 ITMISCOUT Register (Miscellaneous Outputs)
    • 13.4.5 ITMISCIN Register (Miscellaneous Inputs)
    • 13.4.6 Integration Mode Control Register (ITCTRL)
• Cycle Timings and Interlock Behavior
  • 14.1 About cycle timings and interlock behavior
    • 14.1.1 Instruction execution overview
    • 14.1.2 Conditional instructions
    • 14.1.3 Flag-setting instructions
    • 14.1.4 Definition of terms
    • 14.1.5 Assembler language syntax
  • 14.2 Register interlock examples
  • 14.3 Data processing instructions
    • 14.3.1 Cycle counts if destination is not PC
    • 14.3.2 Cycle counts if destination is the PC
    • 14.3.3 Example interlocks
  • 14.4 QADD, QDADD, QSUB, and QDSUB instructions
  • 14.5 Media data-processing
  • 14.6 Sum of Absolute Differences (SAD)
    • 14.6.1 Example interlocks
  • 14.7 Multiplies
  • 14.8 Divide
  • 14.9 Branches
  • 14.10 Processor state updating instructions
  • 14.11 Single load and store instructions
    • 14.11.1 Base register update
  • 14.12 Load and Store Double instructions
  • 14.13 Load and Store Multiple instructions
    • 14.13.1 Load and Store Multiples, other than load multiples including the PC
    • 14.13.2 Load Multiples, where the PC is in the register list
    • 14.13.3 Example Interlocks
  • 14.14 RFE and SRS instructions
  • 14.15 Synchronization instructions
  • 14.16 Coprocessor instructions
  • 14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions
  • 14.18 Miscellaneous instructions
  • 14.19 Floating-point register transfer instructions
  • 14.20 Floating-point load/store instructions
  • 14.21 Floating-point single-precision data processing instructions
  • 14.22 Floating-point double-precision data processing instructions
  • 14.23 Dual issue
    • 14.23.1 Dual issue rules
    • 14.23.2 Permitted combinations
• AC Characteristics
  • 15.1 Processor timing
  • 15.2 Processor timing parameters
    • 15.2.1 Input port timing parameters
    • 15.2.2 Output ports timing parameters
• Processor Signal Descriptions
  • A.1 About the processor signal descriptions
  • A.2 Global signals
  • A.3 Configuration signals
  • A.4 Interrupt signals, including VIC interface signals
  • A.5 L2 interface signals
    • A.5.1 AXI master port
    • A.5.2 AXI master port error detection signals
    • A.5.3 AXI slave port
    • A.5.4 AXI slave port error detection signals
  • A.6 TCM interface signals
  • A.7 Dual core interface signals
  • A.8 Debug interface signals
  • A.9 ETM interface signals
  • A.10 Test signals
  • A.11 MBIST signals
  • A.12 Validation signals
  • A.13 FPU signals
• ECC Schemes
  • B.1 ECC scheme selection guidelines
• Revisions
• Glossary