2 gpio alternate functions, Gpio alternate functions -2, General-purpose i/o block diagram -2 – Intel PXA255 User Manual

Page 106

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4-2

Intel® PXA255 Processor Developer’s Manual

System Integration Unit

When the processor enters sleep mode, the contents of the Power Manager Sleep State registers
(PGSR0, PGSR1 and PGSR2) are loaded into the output data registers. If the particular pin is
programmed as an output, then the value in the PGSR is driven onto the pin before entering sleep
mode. When the processor exits sleep mode, these values remain driven until the GPIO pins are
reprogrammed by writing to the GPDR, GPSR or GPCR, and setting the GPIO bit in the Power
Manager Sleep Status register (PSSR) to indicate that the GPIO registers have been re-initialized
after sleep mode. This is necessary since the GPIO logic loses power during sleep mode

Most GPIO pins can also serve an alternate function within the processor. Certain modes within the
serial controllers and LCD controller require extra pins. These functions are hardwired into specific
GPIO pins and their use is described in the following paragraphs. Even though a GPIO pin is used
for an alternate function, you must still program the proper direction of that pin through the GPDR.
Details on alternate functions are provided in

Section 4.1.2

.

Figure 4-1

shows a block diagram of a

single GPIO pin.

4.1.2

GPIO Alternate Functions

GPIO pins are capable of having as many as six alternate functions that can be set to enable
additional functionality within the processor. If a GPIO is used for an alternate function, then it
cannot be used as a GPIO at the same time. GPIO[0] is reserved because of its special use during
sleep mode and is not available for alternate functions. GPIO[15:0] are used for walk-up from sleep
mode. The walk-up functionality is described in

Section 3.4.9.5, “Exiting Sleep Mode” on page 3-

18

.

Table 4-1

shows each GPIO pin and its corresponding alternate functions.

Figure 4-1. General-Purpose I/O Block Diagram

Edge
Detect

GPIO Pin

Pin Direction

Register

Pin Set and

Clear Registers

Edge Detect

Status Register

Pin-Level

Register

0

Alternate Function

Registers

Rising Edge Detect

Enable Register

Falling Edge Detect

Enable Register

1
2
3

Alternate Functions
(Outputs)

Alternate Functions
(Inputs)

0

1

2

3

Power Manager

Sleep Wake-up logic

2

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