Intel PXA255 - Manual (Page 186)

6-4 Intel® PXA255 Processor Developer’s Manual
Memory Controller
asserted on writes to Variable Latency I/O devices, and nWE is asserted on writes to all other static
devices, both synchronous and asynchronous. For SRAM and variable latency I/O, DQM[3:0] are
byte selects for both reads and writes.
When the processor comes out of reset, it starts fetches and executes instructions at address 0x00,
which corresponds to memory selected by nCS<0>. The boot ROM must be located at this address.
The BOOT_SEL pins determine the type of boot memory (refer to
Section 6.10.1 ).
6.2.3 16-Bit PC Card / Compact Flash Interface
The processor card interface is based on The PC Card Standard - Volume 2 - Electrical
Specification, Release 2.1, and CF+ and CompactFlash Specification Revision 1.4. The 16-bit PC
Card/Compact Flash interface provides control signals to support any combination of 16-bit PC
Card/Compact Flash for two card sockets, using address line (MA[25:0]) and data lines
(MD[15:0]).
The processor 16-bit PC Card / Compact Flash Controller provides the following signals.
• nPREG is muxed with MA[26] and selects register space (I/O or attribute) versus memory
space
• nPOE and nPWE allow memory and attribute reads and writes
• nPIOR, nPIOW, and nIOIS16 control I/O reads and writes
• nPWAIT allows extended access times
• nPCE2 and nPCE1 are byte select high and low for a 16-bit data bus
• PSKTSEL selects between two card sockets
6.3 Memory System Examples
This section provides examples of memory configurations that are possible with the processor.
Figure 6-2 shows a system that uses 1M x 16-bit x 4-bank SDRAM devices for a total of
48 Mbytes.