Intel PXA255 - Manual (Page 16)

xvi Intel® PXA255 Processor Developer’s Manual
Contents
16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single
transfers) .................................................................................................................................16-9
16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10
16-8 National Semiconductor Microwire* Frame Protocol (single transfers) .................................16-10
16-9 Programmable Serial Protocol (multiple transfers) ................................................................16-11
16-10 Programmable Serial Protocol (single transfers) ...................................................................16-12
16-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13
16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14
16-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-14
16-14 National Semiconductor Microwire with SSCR1[TTE]=1 .......................................................16-15
16-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame) .............................16-15
16-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................16-16
16-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to
frame) ....................................................................................................................................16-16
17-1 Example UART Data Frame ....................................................................................................17-3
17-2 Example NRZ Bit Encoding – (0b0100 1011 ...........................................................................17-4
17-3 IR Transmit and Receive Example ..........................................................................................17-9
17-4 XMODE Example. ...................................................................................................................17-9
Tables
2-1 CPU Core Fault Register Bit Definitions....................................................................................2-3
2-2 ID Bit Definitions ........................................................................................................................2-4
2-3 PXA255 Processor ID Values....................................................................................................2-4
2-4 Effect of Each Type of Reset on Internal Register State ...........................................................2-6
2-5 Processor Pin Types .................................................................................................................2-8
2-6 Pin & Signal Descriptions for the PXA255 Processor................................................................2-9
2-7 Pin Description Notes ..............................................................................................................2-17
2-8 System Architecture Register Address Summary ...................................................................2-21
3-1 Core PLL Output Frequencies for 3.6864 MHz Crystal .............................................................3-5
3-2 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................3-5
3-3 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ................................ 3-6
3-4 Power Mode Entry Sequence Table .......................................................................................3-20
3-5 Power Mode Exit Sequence Table .........................................................................................3-20
3-6 Power and Clock Supply Sources and States During Power Modes .....................................3-22
3-7 PMCR Bit Definitions ...............................................................................................................3-23
3-8 PCFR Bit Definitions................................................................................................................3-24
3-9 PWER Bit Definitions ...............................................................................................................3-25
3-10 PRER Bit Definitions................................................................................................................3-26
3-11 PFER Bit Definitions ................................................................................................................3-27
3-12 PEDR Bit Definitions................................................................................................................3-28
3-13 PSSR Bit Definitions................................................................................................................3-29
3-14 PSPR Bit Definitions................................................................................................................3-30
3-15 PMFW Register Bitmap and Bit Definitions .............................................................................3-31
3-16 PGSR0 Bit Definitions .............................................................................................................3-32
3-17 PGSR1 Bit Definitions .............................................................................................................3-32
3-18 PGSR2 Bit Definitions .............................................................................................................3-33
3-19 RCSR Bit Definitions ...............................................................................................................3-34
3-20 CCCR Bit Definitions ...............................................................................................................3-35