Intel PXA255 - Manual (Page 512)

15-10 Intel® PXA255 Processor Developer’s Manual
MultiMediaCard Controller
15.2.8 Data FIFOs
The controller FIFOs for the response tokens, received data, and transmitted data are MMC_RES,
MMC_RXFIFO, and MMC_TXFIFO, respectively. These FIFOs are accessible by the software
and are described in the following paragraphs.
15.2.8.1 Response Data FIFO (MMC_RES)
The response FIFO, MMC_RES, contains the response received from an MMC card after a
command is sent from the controller. MMC_RES is a read only, 16-bit, and 8-entry deep FIFO.
The FIFO will hold all possible response lengths. Responses that are only one byte long are located
on the MSB of the 16-bit entry in the FIFO. The first half-word read from the response FIFO is the
most significant half-word of the received response.
The FIFO does not contain the response CRC. The status of the CRC check is in the status register,
MMC_STAT.
15.2.8.2 Receive Data FIFO, MMC_RXFIFO
The two receive data FIFOs are read only by the software and are readable on a single byte basis.
They are dual FIFOs, where each FIFO is 32 entries of 1-byte data. Access to the FIFOs is
controlled by the controller and depends on the status of the FIFOs.
Both FIFOs and their controls are cleared to a starting state after a system reset and at the
beginning of all command sequences.
The FIFOs swap between the software and MMC bus. At any time, while the software has read
access to one of the FIFOs, the MMC bus has write access to the other FIFO.
For purposes of an example, the FIFOs are called RXFIFO1 and RXFIFO2. After a reset or at the
beginning of a command sequence, both FIFOs are empty and the software has read access to
RXFIFO1 and the MMC has write access to RXFIFO2. When RXFIFO2 becomes full and
RXFIFO1 is empty, the FIFOs swap and the software has read access to RXFIFO2 and the MMC
has write access to RXFIFO1. When RXFIFO1 becomes full and RXFIFO2 is empty, the FIFOs
swap and the software has read access to RXFIFO1 and the MMC has write access to RXFIFO2.
This swapping process continues through out the data transfer and is transparent to both the
software and the MMC controller.
If at any time both FIFOs become full and the data transmission is not complete, the controller
turns the MMCLK off to prevent any overflows. When the clock is off, data transmission from the
card stops until the clock is turned back on. After the software has emptied the FIFO that it is
connected to, the controller turns the clock on to continue data transmission.
The full status of the FIFO that the software is connected to is registered in the
MMC_STAT[RECV_FIFO_FULL] bit.
The receive FIFO is readable on byte boundaries and the FIFO read request is only asserted once
per FIFO access (once per 32 bytes available). Therefore, 32 bytes must be read for each request,
except for the last read which may be less than 32 bytes.