Intel PXA255 - Manual (Page 417)

Intel® PXA255 Processor Developer’s Manual 12-17
USB Device Controller
2. The host PC sends a BULK-OUT.
3. The DMA engine reads data from the EP2 data FIFO (UDDR2).
4. Steps 2 and 3 repeat until all the data has been read from the host.
5. If the software receives an EP2 interrupt it completes the following process:
a. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length
packet.
b. If UDCCS2[RNE] is set, the data packet was a short packet and software must use the
UDCWC2 count register to read the proper amount of data from the EP2 data FIFO
(UDDR2).
c. Software clears the UDCCS2[RPC] bit.
6. Return from interrupt.
12.5.6.2 Software Allows the Megacell to Handle the Transaction
If software allows the Megacell to handle the transaction:
1. During the SETUP VENDOR command, software clears the UDCCS2[DME] bit.
2. The host PC sends a BULK-OUT and the UDC generates an EP2 Interrupt.
3. If UDCCS2[RNE] is clear and UDCCS2[RSP] is set, the data packet was a zero-length packet.
4. If UDCCS2[RNE] is set, software uses the UDCWC2 count register to read the proper amount
of data from the EP2 data FIFO (UDDR2).
5. Software clears the UDCCS2[RPC] bit.
6. Return from interrupt.
7. Steps 2 through 6 repeat until all the data has been read from the host.
12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
The procedure in Case 7 can also be used to operate Endpoints 8 and 13.
In Case 7, the Transmit Short Packet is only set if a packet size of less than 256 bytes is sent. If the
packet size is 256 bytes, the system arms when the 256th byte is loaded. Loading the 256th byte
and setting the UDCCS3[TSP] bit produces one 256-byte packet and one zero-length packet.
When software receives a SETUP VENDOR command to set up an EP3 ISOCHRONOUS IN
transaction, it may take one of three courses of action, as appropriate for the chosen operating
model:
• Configure the DMA engine and disable the EP3 interrupt to allow the DMA engine to handle
the transaction.
• Enable the EP3 interrupt to allow the Megacell to directly handle the transaction.
• Enable the SOF interrupt to handle the transaction on a frame count basis.
12.5.7.1 Software Enables DMA
If software enables the DMA engine to handle the transaction: