Intel PXA255 - Manual (Page 75)

Intel® PXA255 Processor Developer’s Manual 3-13
Clocks and Power Manager
3.4.7.4 Completing the Frequency Change Sequence
The Frequency Change Sequence exits when any Reset is asserted. In Hardware and Watchdog
Resets, the Reset entry and exit sequences take precedence over the Frequency Change Sequence
and the PLL resumes in its Reset condition. In GPIO Reset, the Reset exit sequence is delayed
while the PLL relocks and the frequency is set to the desired frequency of the Frequency Change
Sequence.
If the Watchdog Timer is enabled during the Frequency Change Sequence, set the Watchdog Match
Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is
asserted.
If Hardware or Watchdog Reset is asserted during the Frequency Change Sequence, the DRAM
contents are lost because all states, including Memory Controller configuration and information
about the previous Frequency Change Sequence, are reset. If GPIO Reset is asserted during the
Frequency Change Sequence, the SDRAM contents will be lost during the GPIO Reset exit
sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh
interval.
Normally, the Frequency Change Sequence exits in the following sequence:
1. The processor’s PLL clock generator is reprogrammed with the desired values, which are in
the CCCR, and begins to relock to those values.
Note: This sequence occurs even if the before and after frequencies are the same.
2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the
Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal
Specification for details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either Run or Turbo Mode). Interrupts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency
Change Sequence, software must not immediately clear the FCS bit. The bit must be cleared
on the next required write to the register.
5. Values may be written to the CCCR, but they are ignored until the Frequency Change
Sequence is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring the SDRAM interface.
3.4.8 33-MHz Idle Mode
33-MHz idle mode has the lowest power consumption of any idle mode. The run mode frequency
selected in the Core Clock Configuration Register (CCCR) directly affects the processor idle mode
power consumption. Faster run mode frequencies consume more power. 33-MHz idle mode places
the processor a special low speed run mode before entering idle. This is similar to normal idle since
the CPU core clock can be stopped during periods of processor inactivity and continue to monitor
on- and off-chip interrupt service requests. 33-MHz idle limitations are:
• Peripherals will not function correctly and should be disabled before entering this mode.
• A Frequency Change Sequence must be performed upon entry to and exit from 33-MHz idle
mode.