Intel PXA255 - Manual (Page 442)

12-42 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
12.6.12.4 Endpoint 11 Interrupt Request (IR11)
The interrupt request bit is set if the IM11 bit in the UDC interrupt control register is cleared and
the IN packet complete (TPC) in UDC endpoint 11 control/status register is set. The IR11 bit is
cleared by writing a 1 to it.
12.6.12.5 Endpoint 12 Interrupt Request (IR12)
The interrupt request bit is set if the IM12 bit in the UDC interrupt control register is cleared and
the OUT packet ready bit (RPC) in the UDC endpoint 12 control/status register is set. The IR12 bit
is cleared by writing a 1 to it.
12.6.12.6 Endpoint 13 Interrupt Request (IR13)
The interrupt request bit is set if the IM13 bit in the UDC interrupt control register is cleared and
the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC endpoint 13 control/status
register is set. The IR13 bit is cleared by writing a 1 to it.
12.6.12.7 Endpoint 14 Interrupt Request (IR14)
The interrupt request bit is set if the IM14 bit in the UDC interrupt control register is cleared and
the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC endpoint 14 control/status
register or the Isochronous Error Endpoint 14 (IPE14) in the UFNHR are set. The IR14 bit is
cleared by writing a 1 to it.
12.6.12.8 Endpoint 15 Interrupt Request (IR15)
The interrupt request bit is set if the IM15 bit in the UDC interrupt control is set. The IR15 bit is
cleared by writing a 1 to it.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
12.6.13 UDC Frame Number High Register (UFNHR)
UFNHR, shown in Table 12-24 , holds the three most significant bits of the frame number
contained in the last received SOF packet, the isochronous OUT endpoint error status, and the SOF
interrupt status/interrupt mask bit.