10 udc interrupt control register 1 (uicr1), 10 udc interrupt control register 1 (uicr1) -38, Uicr1 bit definitions -38 – Intel PXA255 User Manual
Page 438
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Intel® PXA255 Processor Developer’s Manual
USB Device Controller
12.6.10
UDC Interrupt Control Register 1 (UICR1)
UICR1, shown in
, contains 8 control bits to enable/disable interrupt service requests
from endpoints 8 - 15. The UICR1 bits are reset to 1 so interrupts are not generated on initial
system reset.
12.6.10.1
Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
The UICR1[IMx] bit is used to mask or enable the corresponding endpoint interrupt request,
USIR1[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the
USIR1 register is not allowed to be set. When the mask bit is cleared and an interruptible condition
occurs in the endpoint, the appropriate interrupt bit is set. Programming the mask bit to a 1 does not
affect the current state of the interrupt bit. It only blocks future zero to one transitions of the
interrupt bit.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 12-21. UICR1 Bit Definitions
0x 4060_0054
UICR1
USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
IM
15
IM
14
IM
13
IM
12
IM
1
1
IM
10
IM
9
IM
8
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
Bits
Name
Description
31:8
—
reserved
7
IM15
Interrupt mask for Endpoint 15
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
6
IM14
Interrupt mask for Endpoint 14
0 = Receive interrupt enabled
1 = Receive interrupt disabled
5
IM13
Interrupt mask for Endpoint 13
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled.
4
IM12
Interrupt mask for Endpoint 12
0 = Receive interrupt enabled
1 = Receive interrupt disabled
3
IM11
Interrupt mask for Endpoint 11
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
2
IM10
Interrupt mask for Endpoint 10
0 = Receive interrupt enabled
1 = Receive interrupt disabled
1
IM9
Interrupt mask for Endpoint 9
0 = Receive interrupt enabled
1 = Receive interrupt disabled
0
IM8
Interrupt Mask for Endpoint 8
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled