Intel PXA255 - Manual (Page 333)

Intel® PXA255 Processor Developer’s Manual 9-5
I
2
C Bus Interface Unit
Figure 9-2 shows the relationship between the SDA and SCL lines for START and STOP
conditions.
9.3.3.1 START Condition
The START condition (ICR[START]=1, ICR[STOP]=0) initiates a master transaction or repeated
START. Before it sets the START ICR bit, software must load the
target slave address and the R/
nW bit in the IDBR (see Section 9.9.2 ). The START and the IDBR contents are transmitted on the
I
2
C bus after the ICR[TB] bit is set. The I
2
C bus stays in master-transmit mode for write requests
and enters master-receive mode for read requests. For a repeated start, a change in read or write, or
a change in the target slave address, the IDBR contains the updated target slave address and the R/
nW bit. A repeated start enables a master to make multiple transfers to different slaves without
surrendering the bus.
The START condition is not cleared by the I
2
C unit. If the I
2
C loses arbitration while initiating a
START, it may re-attempt the START when the bus is freed. See Section 9.4.4 for details on how
the I
2
C unit functions in those circumstances.
9.3.3.2 No START or STOP Condition
The no START or STOP condition (ICR[START]=0, ICR[STOP]=0) is used in master-transmit
mode while the I
2
C unit is transmitting multiple data bytes (see Figure 9-2 ). Software writes the
data byte and the I
2
C unit sets the ISR[ITE] bit and clears the ICR[TB] bit. The software then
writes a new byte to the IDBR and sets the ICR[TB] bit, which initiates the new byte transmission.
This process continues until the software sets the ICR[START] or ICR[STOP] bit. The
ICR[START] and ICR[STOP] bits are not automatically cleared by the I
2
C unit after the
transmission of a START, STOP, or repeated START.
After each byte transfer, including the ICR[ACKNAK] bit, the I 2 C unit holds the SCL line low to
insert wait states until the ICR[TB] bit is set. This action notifies the I
2
C unit to release the SCL
line and allow the next information transfer to proceed.
9.3.3.3 STOP Condition
The STOP condition (ICR[START]=X, ICR[STOP]=1) terminates a data transfer. In master-
transmit mode, the ICR[STOP] bit and the ICR[TB] bit must be set to initiate the last byte transfer
(see
Figure 9-2 ). In master-receive mode, the I
2
C unit must set the ICR[ACKNAK] bit, the
ICR[STOP] bit, and the ICR[TB] bit to initiate the last transfer. Software must clear the
ICR[STOP] condition after it is transmitted.
Figure 9-2. Start and Stop Conditions
SDA
SCL
Start Condition
~ ~
~ ~
~ ~
Stop Condition