Intel PXA255 User Manual

Page 204

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background image

6-22

Intel® PXA255 Processor Developer’s Manual

Memory Controller

1x12x10x16

22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’ 23 9

8

7

6

5

4

3

2

1

1x12x11x32

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

1x12x11x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

1x13x8x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’

9

8

7

6

5

4

3

2

1x13x8x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

1x13x9x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’

24 9

8

7

6

5

4

3

2

1x13x9x16

23 22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’

9

8

7

6

5

4

3

2

1

1x13x10x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’ 25 24 9

8

7

6

5

4

3

2

1x13x10x16

23 22 21 20 19 18 17 16 15 14 13 12 11 10

21 ‘0’ 24 9

8

7

6

5

4

3

2

1

1x13x11x32

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

1x13x11x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x11x8x32

22 21 20 19 18 17 16 15 14 13 12 11 10

22 21 ‘0’

9

8

7

6

5

4

3

2

2x11x8x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x11x9x32

22 21 20 19 18 17 16 15 14 13 12 11 10

22 21 ‘0’

23 9

8

7

6

5

4

3

2

2x11x9x16

22 21 20 19 18 17 16 15 14 13 12 11 10

22 21 ‘0’

9

8

7

6

5

4

3

2

1

2x11x10x32

22 21 20 19 18 17 16 15 14 13 12 11 10

22 21 ‘0’ 24 23 9

8

7

6

5

4

3

2

2x11x10x16

22 21 20 19 18 17 16 15 14 13 12 11 10

22 21 ‘0’ 23 9

8

7

6

5

4

3

2

1

2x11x11x32

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x11x11x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x12x8x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

23 22

‘0’

9

8

7

6

5

4

3

2

2x12x8x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x12x9x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

23 22

‘0’

24 9

8

7

6

5

4

3

2

2x12x9x16

23 22 21 20 19 18 17 16 15 14 13 12 11 10

23 22

‘0’

9

8

7

6

5

4

3

2

1

2x12x10x32

23 22 21 20 19 18 17 16 15 14 13 12 11 10

23 22

‘0’ 25 24 9

8

7

6

5

4

3

2

2x12x10x16

23 22 21 20 19 18 17 16 15 14 13 12 11 10

23 22

‘0’ 24 9

8

7

6

5

4

3

2

1

2x12x11x32

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

2x12x11x16

NOT VALID (illegal addressing combination)

NOT VALID (illegal addressing combination)

Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 2 of 3)

# Bits

Bank x

Row x

Col x

Data

External Address pins at SDRAM RAS Time

MA<24:10>

External Address pins at SDRAM CAS Time

MA<24:10>

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

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