4 dma and program i/o, 3 card communication protocol, Card communication protocol -12 – Intel PXA255 User Manual

Page 514

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15-12

Intel® PXA255 Processor Developer’s Manual

MultiMediaCard Controller

When the DMA is used, it must be programmed to do 1-byte writes of 32-byte bursts. The last
write can be less than a 32-byte burst.

If the last write is less than 32 bytes, then the MMC_PRTBUF[BUF_PART_FULL] bit must be set.
When the DMA is used, the last descriptor must be programmed to allow the DMA to set an
interrupt after the data is written to the FIFO. After the interrupt occurs, the software must set the
MMC_PRTBUF[BUF_PART_FULL] bit.

Some examples are:

Transmit 96 bytes of data:

Write 32 bytes three times.

For the DMA, use three descriptors of 32 bytes and 32-byte bursts.

Transmit 98 bytes of data:

Write 32 bytes three times, then write two more bytes.

For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two
more bytes and 8-, 16- or 32-byte bursts and program the descriptor to set an interrupt, for the
software to write the MMC_PRTBUF[BUF_PART_FULL] bit.

Transmit 105 bytes:

Write 32 bytes three times, then write nine more bytes.

For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of nine
more bytes and 16- or 32-byte bursts and program the descriptor to set an interrupt, for the
software to write MMC_PRTBUF[BUF_PART_FULL] bit.

15.2.8.4

DMA and Program I/O

The software may communicate to the MMC controller via the DMA or program I/O.

To access the FIFOs with the DMA, the software must program the DMA to read or write the
MMC FIFOs with single byte transfers, and 32-byte bursts. For example, to write 64 bytes of data
to the MMC_TXFIFO, the software must program the DMA to write 64 bytes with an 8-bit port
size to the MMC and for 32-byte bursts. The MMC issues a request to read the MMC_RXFIFO and
a request to write the MMC_TXFIFO.

With program I/O, the software waits for the MMC_I_REG[RXFIFO_RD_REQ] or
MMC_I_REG[TXFIFO_WR_REQ] interrupts before reading or writing the respective FIFO.

The CMDAT[DMA_EN] bit must be set to a 1 to enable communication with the DMA and it must
be set to a 0 to enable program I/O.

15.3

Card Communication Protocol

This section discusses the software’s responsibilities and the communication protocols used
between the MMC and the card.

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