Interrupt conditions -10, Iir bit definitions -10, Table 10-8 – Intel PXA255 User Manual
Page 366: Table 10-9
10-10
Intel® PXA255 Processor Developer’s Manual
UARTs
In FIFO mode, the “Received Data is available” interrupt (Priority Level 2) takes priority over the
“Character Timeout Indication” interrupt (Priority Level 2). For example, if the UART is in FIFO
mode and FIFO Control Register[ITL] = 0b00, this will cause the UART to generate an interrupt
when there is one byte in the FIFO. In this scenario, if there is one byte in the FIFO, an interrupt is
generated, and IIR[3:0] = 0b0100, which indicates that Received Data is available. If data remains
in the FIFO and if a Character Timeout occurs (no data has been sent for 4 character times), then
the interrupt status does not change to IIR[3:0] = 0b1100 (Character Timeout Indication).
The error interrupt is reported separately in the LSR. In DMA mode, software must check for the
error interrupt before it checks the IIR.
If additional data is received before a Character Timeout Indication interrupt is serviced, the
interrupt is deasserted.
This is a read-only register. Ignore reads from reserved bits.
Table 10-8. Interrupt Conditions
Priority Level
Interrupt origin
1 (highest)
Receiver Line Status: one or more error bits were set.
2
Received Data is available. In FIFO mode, trigger level was reached. In
non-FIFO mode, RBR has data.
2
Character Timeout Indication occurred. Occurs only in FIFO mode, when
data is in the receive FIFO but no data has been sent for a set time period.
3
Transmitter requests data. In FIFO mode, the transmit FIFO is at least half
empty. In non-FIFO mode, the THR has been transmitted.
4 (lowest)
Modem Status: one or more modem input signal has changed state.
Table 10-9. IIR Bit Definitions (Sheet 1 of 2)
Base+0x8
Interrupt Identification Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
FIFO
ES1
FIFO
ES0
re
s
e
rv
e
d
re
s
e
rv
e
d
IID
3
IID
2
IID
1
IP
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bits
Name
Description
31:8
—
reserved
7:6
FIFOES[1:0]
FIFO Mode Enable Status:
00 – Non-FIFO mode is selected
01 – reserved
10 – reserved
11 – FIFO mode is selected (FCR[TRFIFOE] = 1)
5:4
—
reserved