Intel PXA255 - Manual (Page 418)

12-18 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
1. During the SETUP VENDOR command, software enables the DMA engine and masks the
EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary.
a. If the packet size is 256 bytes, software transfers the all the data in one DMA descriptor.
b. If the packet size is less than 256 bytes, software sets up a string of descriptors in which
the odd numbered descriptors point to the data and the even numbered descriptors are
writes to the UDCCS1[TSP] bit.
2. The host PC sends an ISOC-IN and the UDC sends a data packet back to the host PC.
3. The UDC generates an interrupt that is masked from the Megacell.
4. The DMA engine fills the EP3 data FIFO (UDDR3) with data and sets the UDCCS3[TSP] bit
if the data packet is a short packet.
5. Steps 2 through 4 repeat until all the data has been sent to the host.
12.5.7.2 Software Enables the EP3 Interrupt
If software enables the EP3 interrupt to allow the Megacell to directly handle the transaction:
1. During the SETUP VENDOR command, software fills the EP3 data FIFO (UDDR3) with data
and clears the UDCCS3[TPC] bit. If the data packet is a short packet, software also sets the
UDCCS3[TSP] bit.
2. The host PC sends a ISOC-IN command and the UDC sends a data packet back to the host PC
and generates an EP3 Interrupt.
3. Software fills the EP3 data FIFO (UDDR3) with data and clears the UDCCS3[TPC] bit. If the
data packet is a short packet, software also sets the UDCCS3[TSP] bit.
4. Return from interrupt.
5. Steps 2 through 4 repeat until all of the data is sent to the host PC.
12.5.7.3 Software Enables the SOF Interrupt
If software enables the SOF interrupt to handle the transaction on a frame count basis:
1. Software disables the UDCCS3 Interrupt by setting UICR0[IM3] to a 1 and enables the SOF
interrupt in the UFNHR register by setting UFNHR[SIM] to a 0.
2. When the host PC sends an SOF, the UDC sets the UFNHR[SIR] bit, which causes an SOF
interrupt.
3. Software checks the UDCCS3[TFS] bit to determine if there is room for a data packet. If there
is room, software fills the EP3 data FIFO (UDDR3) with data and clears the UDCCS3[TPC]
bit. If the data packet is a short packet, software sets the UDCCS3[TSP] bit.
4. Software clears the UFNHR[SIR] bit.
5. Return from interrupt.
6. Steps 2 through 5 repeat until all the data is sent to the host PC.
12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
The procedure in Case 8 can also be used to operate Endpoints 9 and 14.