Intel PXA255 - Manual (Page 40)

2-10 Intel® PXA255 Processor Developer’s Manual
System Architecture
SDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always deasserted upon reset. Driven Low Driven Low
SDCLK[2] OC Driven Low Driven Low
nCS[5]/
GPIO[33]
ICOCZ
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Hi-Z - Note [1] Note [4]
nCS[4]/
GPIO[80]
ICOCZ
nCS[3]/
GPIO[79]
ICOCZ
nCS[2]/
GPIO[78]
ICOCZ
nCS[1]/
GPIO[15]
ICOCZ
nCS[0] ICOCZ
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Driven High Note [4]
RD/nWR OCZ
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Driven Low Holds last state
RDY/
GPIO[18]
ICOCZ
Variable Latency I/O Ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
Hi-Z - Note [1] Note [3]
L_DD[8]/
GPIO[66]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller. Hi-Z - Note [1] Note [3]
L_DD[15]/
GPIO[73]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Hi-Z - Note [1] Note [3]
MBGNT/
GP[13]
ICOCZ
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Hi-Z - Note [1] Note [3]
MBREQ/
GP[14]
ICOCZ
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
Hi-Z - Note [1] Note [3]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
ICOCZ
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
Hi-Z - Note [1] Note [5]
nPWE/
GPIO[49]
ICOCZ
PCMCIA write enable. (output) Performs writes to
PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for Variable Latency I/O.
Hi-Z - Note [1] Note [5]
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State