5 lcd dma command registers (ldcmdx), Section 7.6.5.5 – Intel PXA255 User Manual
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Intel® PXA255 Processor Developer’s Manual
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LCD Controller
7.6.5.5
LCD DMA Command Registers (LDCMDx)
LDCMDx, shown in
, correspond to DMA channels 0 and 1 and contain configuration
fields and the length of the current descriptor for the DMA channel. On reset, the bits in these
register are initialized to zero. Reserved bits must be written with zeros and reads from reserved
bits must be ignored.
These read-only registers are loaded indirectly via the frame descriptors, as described in
Load Palette (PAL) — indicates that data being fetched will be loaded into the palette RAM. If
PAL is set to one, the palette RAM is loaded with the first 8, 32, or 512-bytes of data as follows:
8 bytes for 1 and 2-bit pixels
32 bytes for 4-bit pixels
512 bytes for 8-bit pixels.
Software must load the palette at least once after enabling the LCD. Otherwise, the palette entries
will not be initialized, and the frame data will not have a valid frame palette to reference.
The palette must not be loaded if the LCD is operating in 16-bit pixel mode.
Note:
The PAL bit must never be set in LDCMD1, since the palette is always loaded with Channel 0.
Start Of Frame Interrupt (SOFINT) — when set, the DMAC sets the start of frame bit
(LCSR[SOF]) when starting a new frame. The SOF bit is set after a new descriptor is loaded from
memory and before the palette/frame data is fetched.
In dual-panel mode, LCSR[SOF] is set only when both channels reach the start of frame and both
frame descriptors have SOFINT set. SOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
End Of Frame Interrupt (EOFINT) — when set, the DMAC sets the end of frame bit
(LCSR[EOF]) after fetching the last word in the frame buffer.
In dual-panel mode, LCSR[EOF] is set only when both channels reach the end of frame and both
frame descriptors have EOFINT set. EOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
Transfer Length (LEN) — determines the number of bytes fetched by the DMAC. LEN = 0 is not
valid. If PAL is set to one, LEN must be programmed with the size of the palette RAM. This
corresponds to:
8 bytes for 1 and 2-bit pixels (only the top 2 entries are actually used for 1-bit pixels)
32 bytes for 4-bit pixels
512 bytes for 8-bit pixels.
Note:
A separate descriptor must be used to fetch the frame data.
The value of LEN for frame data is a function of the screen size and the pixel size and it must be
consistent with the values used for LCCR1[PPL], LCCR2[LPP], and LCCR3[BPP]. See
for instructions on calculating length. The LCD DMAC decrements LEN as it fetches
data, allowing the user to read the number of bytes remaining for the current descriptor.
These are read-only registers. Ignore reads from reserved bits.