Intel PXA255 - Manual (Page 524)

15-22 Intel® PXA255 Processor Developer’s Manual
MultiMediaCard Controller
• Set MMC_BLKLEN register to the number of bytes per block.
• Update the MMC_CMDAT register as:
— Write 0x01 to the MMC_CMDAT[RESPONSE_FORMAT].
— Set the MMC_CMDAT[DATA_EN] bit.
— Clear the MMC_CMDAT[WRITE/READ] bit.
— Set the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
• Turn the clock on.
After it turns the clock on, the software must perform these steps:
1. Wait for the response as described in Section 15.4.4 .
2. Read data from the MMC_RXFIFO FIFO and continue until all of the data has been read from
the FIFO.
3. Set the command registers for a stop transaction command (CMD12). If the DMA is being
used, the last descriptor must set the DMA to send an interrupt to signal that all the data has
been read.
4. Wait for a response to the stop transaction command as described in Section 15.4.4 .
5. Set MMC_I_MASK to 0x1e.
6. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
7. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
15.5 MMC Controller Registers
The MMC controller is controlled by a set of registers that software configures before every
command sequence on the MMC bus.
Table 15-5 through Table 15-23 describe the registers and FIFOs.
15.5.1 MMC_STRPCL Register
The MMC_STRPCL, shown in Table 15-5 , allows the software to start and stop the MMC bus
clock. Reads from this register are unpredictable.
This is a write-only register. Write zeros to reserved bits.