3 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) – Intel PXA255 User Manual
Page 425: Udccs0 bit definitions -25
Intel® PXA255 Processor Developer’s Manual
12-25
USB Device Controller
12.6.3
UDC Endpoint 0 Control/Status Register (UDCCS0)
UDCCS0, shown in
, contains seven bits that are used to operate endpoint zero, the
control endpoint.
12.6.3.1
OUT Packet Ready (OPR)
The OUT packet ready bit is set by the UDC when it receives a valid OUT packet to endpoint zero.
When this bit is set, the USIR0[IR0] bit will be set in the UDC status/interrupt register if endpoint
zero interrupts are enabled. This bit is cleared by writing a one. The UDC is not allowed to enter
the data phase of a transaction until this bit is cleared.
12.6.3.2
IN Packet Ready (IPR)
The IN packet ready bit is set by the core if less than max_packet bytes (16) have been written to
the endpoint 0 FIFO to be transmitted. The core must not set this bit if a max_packet is to be
transmitted. The UDC clears this bit when the packet has been successfully transmitted, the
UDCCS0[FTF] bit has been set, or a control OUT is received. When this bit is cleared due to a
successful IN transmission or the reception of a control OUT, the USIR0[IR0] bit in the UDC
interrupt register is set if the endpoint 0 interrupt is enabled via UICR0[IM0]. The Intel® XScale™
microarchitecture is not able to clear UDCCS0[IPR] and always reads back a zero
Table 12-14. UDCCS0 Bit Definitions
0x 4060_0010
UDCCS0
USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
SA
RN
E
FS
T
SS
T
DRW
F
FT
F
IPR
OP
R
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
Bits
Name
Description
0
OPR
OUT packet ready (read/write 1 to clear)
0 = OUT packet ready.
1
IPR
IN packet ready (always read 0/write 1 to set).
1 = IN packet ready.
2
FTF
Flush Tx FIFO (always read 0/write 1 to set)
1 = Flush the contents of Tx FIFO.
3
DRWF
Device remote wakeup feature (read-only)
0 = Device Remote Wakeup Feature is disabled.
1 = Device Remote Wakeup Feature is enabled.
4
SST
Sent stall (read/write 1 to clear).
1 = UDC sent stall handshake
5
FST
Force stall (read/write 1 to set).
1 = Force stall handshake
6
RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
7
SA
Setup Active (read/write 1 to clear)
1 = Setup command is active on the USB
31:8 —
reserved