3 dmac registers, 1 dma interrupt register (dint), 2 dma channel control/status register (dcsrx) – Intel PXA255 User Manual
Page 167: Dmac registers -17 5.3.1, Dma interrupt register (dint) -17, Dma channel control/status register (dcsrx) -17, Dint bit definitions -17, N in, Table 5-6, Section 5.3.1
Intel® PXA255 Processor Developer’s Manual
5-17
DMA Controller
5.3
DMAC Registers
The section describes the DMAC registers.
5.3.1
DMA Interrupt Register (DINT)
The DINT, shown in
, logs the interrupts for each channel.
An interrupt is generated if any of these events occur:
•
Any kind of transaction error on the internal bus that is associated with the relevant channel.
•
The current transfer finishes successfully and the DCMD[ENDIRQEN] bit is set.
•
The current descriptor loads successfully and the DCMD[STARTIRQEN] bit is set.
•
The DCSR:STOPIRQEN is set to a 1 and the relevant channel is in the uninitialized or stopped
state.
Software must set the corresponding DCSR register error bit to reset the interrupt.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
5.3.2
DMA Channel Control/Status Register (DCSRx)
contains the control and status bit for each channel. Read this
register to find the source of an interrupt. Write the read value back to the register to clear the
interrupt.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 5-6. DINT Bit Definitions
Physical Address
0x4000_00F0
DMA Interrupt Register (DINT)
DMA Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
C
h
lInt
r15
C
h
lInt
r14
C
h
lInt
r13
C
h
lInt
r12
Ch
lI
n
tr1
1
C
h
lInt
r10
C
h
lInt
r9
C
h
lInt
r8
C
h
lInt
r7
C
h
lInt
r6
C
h
lInt
r5
C
h
lInt
r4
C
h
lInt
r3
C
h
lInt
r2
C
h
lInt
r1
C
h
lInt
r0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:16
—
reserved
15:0
CHLINTRx
Channel ‘x’ Interrupt (read-only).
0 –
No interrupt
1 – Interrupt