Sxcnfg bit definitions -33 – Intel PXA255 User Manual
Page 215
Intel® PXA255 Processor Developer’s Manual
6-33
Memory Controller
Table 6-13. SXCNFG Bit Definitions (Sheet 1 of 4)
0x4800_001C
SXCNFG
Memory Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
re
s
e
rv
e
d
S
X
LA
TC
H
2
SX
T
P
2
SX
CA
2
SX
RA
2
SXRL2
SXCL2
S
XEN
2
re
s
e
rv
e
d
S
X
LA
TC
H
0
SX
T
P
0
SX
CA
0
SX
RA
0
SXRL0
SXCL0
S
XEN
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
Bits
Name
Description
31
—
reserved
30
SXLATCH2
SXMEM latching scheme for pair 2/3
0 – Latch return data with fixed delay on MEMCLK
1 – Latch return data with return clock
Must be set to a 1 to enable the return clock SDCLK for latching data. For more details on
this return data latching, see
29:28
SXTP2
SX Memory type for partition pair 2/3
00 – Synchronous Mask ROM (SMROM)
01 – reserved
10 – non-SDRAM-like Synchronous Flash
11 – reserved
27:26
SXCA2
SX Memory column address bit count for partition pair 2/3
00 – 7 column address bits
01 – 8 column address bits
10 – 9 column address bits
11 – 10 column address bits
25:24
SXRA2
SX Memory row address bit count for partition pair 2/3
00 – 12 row address bits
01 – 13 row address bits
10 – reserved
11 – reserved
23:21
SXRL2
RAS Latency for SX Memory partition pair 2/3.
Number of external SDCLK cycles between receiving the ACT command and the READ
command. The unit size for SXRL2 is the external SDCLK cycle.
IF SXTP2 = “00” (SMROM):
000 – 1 clock
001 – 2 clocks
010 – 3 clocks
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – 7 clocks
111 – 8 clocks
IF SXTP2 = 10 (non-SDRAM timing Fast Flash), this field is not used and must be
programmed to 111.