Intel PXA255 - Manual (Page 173)

Intel® PXA255 Processor Developer’s Manual 5-23
DMA Controller
5.3.7 DMA Command Registers (DCMDx)
For software, DCMDx ( Table 5-12 ) is read only in Descriptor Fetch Mode and is read/write in No-
Descriptor Fetch Mode.
These registers contain the channel’s control bits and the length of the current transfer in that
channel. On power up, the bits in this register are set to 0.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 5-11. DTADRx Bit Definitions
0x4000_02x8
DMA Target Addr Register
(DTADRx)
DMA Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARGET ADDRESS
reser
v
e
d
Reset Uninitialized
Bits Name Description
31:3 TRGADDR
Target Address (read / write):
Address of the on chip peripheral or the address of a memory location
Address of a memory location for companion chip transfer
2 TRGADDR
Target Address Bit 2
Reserved if DTADR.TrgAddr is an external memory location
Not reserved if DTADR.trgAddr is an internal peripheral (read / write).
1:0 — reserved