Intel PXA255 - Manual (Page 27)

Intel® PXA255 Processor Developer’s Manual 1-3
Introduction
1.2.4 DMA Controller (DMAC)
The DMAC provides sixteen prioritized channels to service transfer requests from internal
peripherals and up to two data transfer requests from external companion chips. The DMAC is
descriptor-based to allow command chaining and looping constructs.
The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-to-
peripheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use
word, half-word, or byte data sizes.
1.2.5 LCD Controller
The LCD Controller supports both passive (DSTN) and active (TFT) flat-panel displays with a
maximum supported resolution of 640x480x16-bit/pixel. An internal 256 entry palette expands 1,
2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.
Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel
displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
1.2.6 AC97 Controller
The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at
sample rates up to 48 KHz. The controller provides independent 16-bit channels for Stereo PCM
In, Stereo PCM Out, Modem In, Modem Out, and mono Microphone In. Each channel includes a
FIFO that supports DMA access to memory.
1.2.7 Inter-IC Sound (I
2
S) Controller
The I
2
S Controller provides a serial link to standard I
2
S CODECs for digital stereo sound. It
supports both the Normal-I
2
S and MSB-Justified I
2
S formats, and provides four signals for
connection to an I
2
S CODEC. I
2
S Controller signals are multiplexed with AC97 Controller pins.
The controller includes FIFOs that support DMA access to memory.
1.2.8 Multimedia Card (MMC) Controller
The MMC Controller provides a serial interface to standard memory cards. The controller supports
up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC
controller has FIFOs that support DMA access to and from memory.
1.2.9 Fast Infrared (FIR) Communication Port
The FIR Communication Port is based on the 4-Mbps Infrared Data Association (IrDA)
Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR
Communication Port uses the STUART’s transmit and receive pins to directly connect to external
IrDA LED transceivers.